公开(公告)号：US09984915B2

公开(公告)日：2018-05-29

申请号：US14291107

申请日：2014-05-30

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: H01L21/762 ,  H01L29/06 ,  C23C14/06 ,  C23C14/34 ,  H01L29/40 ,  C23C14/58 ,  C23C14/35 ,  H01L29/16 ,  H01L21/02 ,  H01L29/73

CPC classification number: H01L21/762 ,  C23C14/0605 ,  C23C14/345 ,  C23C14/35 ,  C23C14/5806 ,  H01L21/02527 ,  H01L21/02631 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/408 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

公开(公告)号：US20170243963A1

公开(公告)日：2017-08-24

申请号：US15589352

申请日：2017-05-08

Applicant: Infineon Technologies AG

Inventor： Daniel Schloegl ,  Johannes Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/36 ,  H01L21/02 ,  H01L29/06 ,  H01L29/861 ,  H01L29/868 ,  H01L29/66 ,  H01L21/266 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7395 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/266 ,  H01L21/283 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/6609 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/868

Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

公开(公告)号：US12211703B2

公开(公告)日：2025-01-28

申请号：US18236434

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/265 ,  H01L21/78

Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

公开(公告)号：US20230275033A1

公开(公告)日：2023-08-31

申请号：US18109616

申请日：2023-02-14

Applicant: Infineon Technologies AG

Inventor： Thomas Huber ,  Matthias Kuenle ,  Iris Moder ,  Joerg Ortner

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: A semiconductor substrate includes a semiconductor base substrate. An alignment structure is formed on a surface of the semiconductor base substrate. An epitaxial layer is deposited on the surface of the semiconductor base substrate. The alignment structure includes an area of the surface of the semiconductor base substrate that is formed as a groove pattern. Grooves of the groove pattern are aligned with a specific crystallographic direction of the semiconductor base substrate. The specific crystallographic direction provides for a slower epitaxial growth rate on such a groove-patterned base substrate surface area compared to epitaxial growth on a surface of the semiconductor base substrate adjacent to the groove-patterned area.

公开(公告)号：US10325803B2

公开(公告)日：2019-06-18

申请号：US15969868

申请日：2018-05-03

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: C23C14/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/16 ,  H01L29/06 ,  H01L29/40 ,  C23C14/58 ,  C23C14/34 ,  C23C14/35 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

公开(公告)号：US20190165151A1

公开(公告)日：2019-05-30

申请号：US16202567

申请日：2018-11-28

Applicant: Infineon Technologies AG

Inventor： Oana Julia Spulber ,  Matthias Kuenle ,  Wolfgang Roesner ,  Christian Philipp Sandow ,  Christoph Weiss

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265

Abstract: An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 1013 cm−3 along a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.

公开(公告)号：US20190157401A1

公开(公告)日：2019-05-23

申请号：US16235726

申请日：2018-12-28

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Daniel Schloegl ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/36 ,  H01L29/861 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/36 ,  H01L21/265 ,  H01L29/0804 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66674 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/861

Abstract: A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*1015 cm−3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*1022 cm−4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.

公开(公告)号：US20190035909A1

公开(公告)日：2019-01-31

申请号：US16050163

申请日：2018-07-31

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Johannes Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Daniel Schloegl

IPC: H01L29/66 ,  H01L21/02 ,  C30B15/00 ,  C30B15/20

Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.

公开(公告)号：US09647083B2

公开(公告)日：2017-05-09

申请号：US15142992

申请日：2016-04-29

Applicant: Infineon Technologies AG

Inventor： Daniel Schloegl ,  Johannes Baumgartl ,  Matthias Kuenle ,  Erwin Lercher ,  Hans-Joachim Schulze ,  Christoph Weiss

IPC: H01L29/74 ,  H01L31/111 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/283 ,  H01L21/265

CPC classification number: H01L29/7395 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/265 ,  H01L21/266 ,  H01L21/283 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/6609 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/861 ,  H01L29/868

Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

公开(公告)号：US20150348824A1

公开(公告)日：2015-12-03

申请号：US14291107

申请日：2014-05-30

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: H01L21/762 ,  H01L29/40 ,  C23C14/06 ,  C23C14/35 ,  C23C14/58 ,  H01L29/06 ,  C23C14/34

CPC classification number: H01L21/762 ,  C23C14/0605 ,  C23C14/345 ,  C23C14/35 ,  C23C14/5806 ,  H01L21/02527 ,  H01L21/02631 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/408 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

Abstract translation: 根据各种实施例，半导体晶片可以包括：包括集成电路结构的半导体本体; 以及至少一个四面体无定形碳层，形成在所述集成电路结构中的至少一个或所述集成电路结构中的至少一个，所述至少一个四面体非晶碳层可以包括大于约0.4的sp3-杂化碳的物质量分数和大于约0.4的物质量分数 的氢小于约0.1。