公开(公告)号：US20190043557A1

公开(公告)日：2019-02-07

申请号：US16001869

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G06F3/06 ,  G11C7/10

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20190042131A1

公开(公告)日：2019-02-07

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Christopher E. COX ,  Navneet DOUR ,  Asaf RUBINSTEIN ,  Israel DIAMAND

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US20180130506A1

公开(公告)日：2018-05-10

申请号：US15804920

申请日：2017-11-06

Applicant: Intel Corporation

Inventor： Uksong KANG ,  Christopher E. COX

IPC: G11C7/10 ,  G11C11/406 ,  G11C7/22 ,  G11C11/408

CPC classification number: G11C7/10 ,  G06K9/00006 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/10 ,  G11C2207/229 ,  H04L29/06

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US20160300606A1

公开(公告)日：2016-10-13

申请号：US15181358

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Christopher E. COX ,  Kuljit Singh BAINS ,  John B. HALBERT

IPC: G11C11/406 ,  G11C11/409

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract translation: 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US20230386548A1

公开(公告)日：2023-11-30

申请号：US18213231

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G11C11/4096 ,  G06F3/0673 ,  G06F3/0659 ,  G06F3/0619 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20210232504A1

公开(公告)日：2021-07-29

申请号：US17227220

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Christopher E. COX ,  Nikhil TALPALLIKAR

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/1081 ,  G06F12/1009 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32

Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.

公开(公告)号：US20210020224A1

公开(公告)日：2021-01-21

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20200286543A1

公开(公告)日：2020-09-10

申请号：US16741368

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Christopher P. MOZAK ,  Christopher E. COX ,  Yan FU ,  Robert J. FRIAR ,  Hsien-Pao YANG

IPC: G11C11/4072 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G06F13/16

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US20190392886A1

公开(公告)日：2019-12-26

申请号：US16340084

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4076

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20190103154A1

公开(公告)日：2019-04-04

申请号：US15721052

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/4076 ,  G11C11/409 ,  G11C7/22 ,  G06F12/06

CPC classification number: G11C11/4076 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1673 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/06 ,  G11C11/409

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.