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    Electronic device package
    21.
    发明授权
    Electronic device package 有权

    公开(公告)号：US10403578B2

    公开(公告)日：2019-09-03

    申请号：US15721788

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Digvijay A. Raorane ,  Vipul V. Mehta

    IPC: H01L23/12 ,  H01L23/053 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.

    Embedded bridge with through-silicon vias
    24.
    发明授权
    Embedded bridge with through-silicon vias 有权

    公开(公告)号：US10373893B2

    公开(公告)日：2019-08-06

    申请号：US15640406

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

    Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

    Electronic package assembly with compact die placement
    25.
    发明授权
    Electronic package assembly with compact die placement 有权

    公开(公告)号：US10373888B2

    公开(公告)日：2019-08-06

    申请号：US15395985

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Eric J. Li ,  Vipul V. Mehta ,  Digvijay A. Raorane

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

    Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

    Die sidewall interconnects for 3D chip assemblies
    26.
    发明授权
    Die sidewall interconnects for 3D chip assemblies 有权

    公开(公告)号：US10199354B2

    公开(公告)日：2019-02-05

    申请号：US15385673

    申请日：2016-12-20

    Applicant: INTEL CORPORATION

    Inventor： Mitul Modi ,  Digvijay A. Raorane

    IPC: H01L25/065 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/78 ,  H01L23/00

    Abstract: A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.

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