公开(公告)号：US10289514B2

公开(公告)日：2019-05-14

申请号：US14319197

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Eric Distefano ,  James G. Hermerding, II ,  Esfir Natanzon

IPC: G06F11/30 ,  G06F11/34 ,  G06F1/324 ,  G06F1/3296 ,  G01R31/28

Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

公开(公告)号：US20180059763A1

公开(公告)日：2018-03-01

申请号：US15250123

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J Ragland ,  Ofer Nathan ,  Nadav Shulman ,  Esfir Natanzon

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

公开(公告)号：US09904339B2

公开(公告)日：2018-02-27

申请号：US14482148

申请日：2014-09-10

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

公开(公告)号：US09710043B2

公开(公告)日：2017-07-18

申请号：US14554628

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu Salah ,  Efraim Rotem ,  Guy M. Therien ,  Nadav Shulman ,  Esfir Natanzon ,  Paul S. Diefenbaugh

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

公开(公告)号：US09250906B2

公开(公告)日：2016-02-02

申请号：US14840014

申请日：2015-08-30

Applicant: Intel Corporation

Inventor： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/00

CPC classification number: G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.