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公开(公告)号：US10360098B2
公开(公告)日：2019-07-23
申请号：US15264680
申请日：2016-09-14
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
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公开(公告)号：US10204064B2
公开(公告)日：2019-02-12
申请号：US15692613
申请日：2017-08-31
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
IPC: G06F13/00 , G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46
Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
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公开(公告)号：US10140240B2
公开(公告)日：2018-11-27
申请号：US15393518
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson
Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
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公开(公告)号：US20180060259A1
公开(公告)日：2018-03-01
申请号：US15669197
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Brian S. Morris , Bill Nale , Robert G. Blankenship , Jeffrey C. Swanson
CPC classification number: G06F13/28 , G06F13/1642 , G06F13/382 , G06F13/4221
Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
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公开(公告)号：US09740654B2
公开(公告)日：2017-08-22
申请号：US14583554
申请日：2014-12-26
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson
CPC classification number: G06F13/4221 , G06F13/4265 , H03M13/09
Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
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Patent Agency Ranking
公开(公告)号：US09740646B2
公开(公告)日：2017-08-22
申请号：US14578407
申请日：2014-12-20
Applicant: Intel Corporation
Inventor： Brian S. Morris , Bill Nale , Robert G. Blankenship , Jeffrey C. Swanson
CPC classification number: G06F13/28 , G06F13/1642 , G06F13/382 , G06F13/4221
Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
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公开(公告)号：US20170109315A1
公开(公告)日：2017-04-20
申请号：US15393153
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US09507746B2
公开(公告)日：2016-11-29
申请号：US13976966
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson
CPC classification number: G06F13/4221 , G06F13/4265 , H03M13/09
Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
Abstract translation: 生成链路层控制消息并将其包含在要通过串行数据链路发送到设备的飞行中。 通过数据链路发送的闪烁将包括多个时隙。 在一些方面，控制消息可以包括病毒警报消息，毒药警报消息，信用返回消息和确认。
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公开(公告)号：US12197357B2
公开(公告)日：2025-01-14
申请号：US17556853
申请日：2021-12-20
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/77 , G06F9/30 , G06F9/445 , G06F9/46 , G06F11/10 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/40 , G06F13/42 , H04L9/06 , H04L49/15 , G06F8/73 , H04L12/46 , H04L45/74
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US20240012772A1
公开(公告)日：2024-01-11
申请号：US18347236
申请日：2023-07-05
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
CPC classification number: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/4286 , G06F8/71 , G06F8/77 , G06F9/30145 , G06F13/4221 , G06F12/0806 , G06F12/0833 , G06F9/466 , G06F13/4022 , G06F9/44505 , G06F13/4282 , G06F1/3287 , G06F13/4068 , G06F11/1004 , G06F13/4291 , H04L9/0662 , G06F12/0808 , H04L45/74
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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