公开(公告)号：US10453705B2

公开(公告)日：2019-10-22

申请号：US15865471

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Sameer Shekhar ,  Kaladhar Radhakrishnan

IPC: H01L21/56 ,  H01F17/04 ,  H02J50/10 ,  H01F27/24 ,  H01L23/64 ,  H01L21/48 ,  H01F17/00 ,  H05K1/16 ,  H05K1/02

Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.

公开(公告)号：US10014692B2

公开(公告)日：2018-07-03

申请号：US14575900

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Sameer Shekhar

IPC: H01F5/00 ,  H03H7/00 ,  H02J4/00 ,  H03H7/48 ,  H03H7/09

CPC classification number: H02J4/00 ,  H01F5/00 ,  H03H1/0007 ,  H03H7/00 ,  H03H7/09 ,  H03H7/1725 ,  H03H7/48 ,  H03H2001/0078

Abstract: Embodiments include apparatuses, methods, and systems with cross-coupling noise reduction in circuits. In embodiments, a circuit may include a common inductor and a negatively coupled inductor pair connected or coupled between the first inductor and a first load and a second load. The negatively coupled inductor pair may include a first and a second inductor. The first inductor may be connected or coupled to the first load and the second inductor may be connected or coupled to the second load to reduce cross-coupling noise between the first load and the second load. Examples of passive structures that may be used to implement the circuit are also described. Other embodiments may also be described and claimed.

公开(公告)号：US20160371216A1

公开(公告)日：2016-12-22

申请号：US14742695

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain

IPC: G06F13/40 ,  G06F1/26

CPC classification number: G06F13/4068 ,  G06F1/26 ,  H01L23/642 ,  H01L25/16 ,  H05K1/0231 ,  H05K1/162 ,  H05K2201/10015

Abstract: Methods and apparatus relating to capacitor interconnections and/or volume re-capture for voltage noise reduction are described. In an embodiment, an interconnection capacitor is coupled to voltage regulator logic. The interconnection capacitor provides substrate decoupling for a plurality of loads. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与电容器互连和/或电压噪声降低的体积再捕获有关的方法和装置。 在一个实施例中，互连电容器耦合到电压调节器逻辑。 互连电容器为多个负载提供衬底去耦。 还公开并要求保护其他实施例。

公开(公告)号：US20240329715A1

公开(公告)日：2024-10-03

申请号：US18129138

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Howard L. Heck ,  Marva Mason Ortiz ,  Stephen Harvey Hall ,  Eskinder Hailu ,  Chin Lee Kuan ,  Sameer Shekhar

IPC: G06F1/3215 ,  G06F1/324

CPC classification number: G06F1/3215 ,  G06F1/324

Abstract: An apparatus, system, and method for improved power consumption and/or noise reduction in a differential input/output (I/O) buffer are provided. A circuit can include a differential signal buffer and encoding scheme quantifying and selection circuitry. The encoding scheme quantifying and selection circuitry can be configured to generate a selection code indicating a selected encoding scheme of the encoding schemes based on respective signals indicating whether each respective encoding scheme of encoding schemes has a net positive power consumption reduction in differential signals. The encoding scheme quantifying and selection circuitry can be configured to provide the selection code to an encoder.

公开(公告)号：US12057433B2

公开(公告)日：2024-08-06

申请号：US16910014

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit Jain

IPC: H01L25/065 ,  H01L23/427 ,  H01L23/552 ,  H01L49/02 ,  H03H1/00 ,  H03H7/01

CPC classification number: H01L25/0652 ,  H01L23/427 ,  H01L23/552 ,  H01L28/10 ,  H01L28/60 ,  H03H1/0007 ,  H03H7/0115 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H03H2001/0078

Abstract: Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

公开(公告)号：US11562963B2

公开(公告)日：2023-01-24

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Sameer Shekhar ,  Amit Jain

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

公开(公告)号：US11429172B2

公开(公告)日：2022-08-30

申请号：US16735563

申请日：2020-01-06

Applicant: Intel Corporation

Inventor： Alexander Uan-Zo-Li ,  Eugene Gorbatov ,  Harish Krishnamurthy ,  Alexander Lyakhov ,  Patrick Leung ,  Stephen Gunther ,  Arik Gihon ,  Khondker Ahmed ,  Philip Lehwalder ,  Sameer Shekhar ,  Vishram Pandit ,  Nimrod Angel ,  Michael Zelikson

IPC: G06F1/32 ,  G05F1/56

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

公开(公告)号：US11342852B2

公开(公告)日：2022-05-24

申请号：US15631996

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Alexander Waizman ,  Michael Zelikson ,  Chin Lee Kuan

IPC: H02M3/158 ,  H02M3/335 ,  G05F1/46 ,  H02M1/36 ,  H02M3/24

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

公开(公告)号：US11175709B2

公开(公告)日：2021-11-16

申请号：US16551523

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Mark Carbone ,  Merwin M. Brown

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

公开(公告)号：US20210335712A1

公开(公告)日：2021-10-28

申请号：US17371293

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.