公开(公告)号：US10903818B2

公开(公告)日：2021-01-26

申请号：US15089001

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Feras Eid ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Valluri R. Rao ,  Johanna M. Swan

IPC: H03H9/54 ,  H03H9/05 ,  H03H9/58 ,  G06F1/18 ,  H03H9/56

Abstract: Embodiments of the invention include a piezoelectric package integrated filtering device that includes a film stack. In one example, the film stack includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The film stack is suspended with respect to a cavity of an organic substrate having organic material and the film stack generates an acoustic wave to be propagated across the film stack in response to an application of an electrical signal between the first and second electrodes.

公开(公告)号：US20200286789A1

公开(公告)日：2020-09-10

申请号：US16884099

申请日：2020-05-27

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Valluri R. Rao ,  Han Wui Then

IPC: H01L21/8258 ,  H01L29/778 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L21/762 ,  H01L27/06

Abstract: A complementary metal oxide semiconductor (CMOS) device that includes a gallium nitride n-type MOS and a silicon P-type MOS is disclosed. The device includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode. The device further includes a silicon/polysilicon layer formed over the gallium nitride transistor.

公开(公告)号：US10707136B2

公开(公告)日：2020-07-07

申请号：US16078663

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Valluri R. Rao ,  Han Wui Then

IPC: H01L21/8258 ,  H01L29/778 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L21/762 ,  H01L27/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/417

Abstract: This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.

公开(公告)号：US10432167B2

公开(公告)日：2019-10-01

申请号：US15088814

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Baris Bicen ,  Telesphor Kamgaing ,  Vijay K. Nair ,  Johanna M. Swan ,  Georgios C. Dogiamis ,  Valluri R. Rao

IPC: H03H9/17 ,  H03H9/02 ,  H03H9/24 ,  H03H9/15

Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.

公开(公告)号：US10256286B2

公开(公告)日：2019-04-09

申请号：US15589981

申请日：2017-05-08

Applicant: INTEL CORPORATION

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01F5/00 ,  H01F27/06 ,  G09G5/00 ,  H01L49/02 ,  H01F7/06 ,  H01L23/48 ,  H01L23/522 ,  H01F17/00 ,  H01L21/768 ,  H01L27/06 ,  H01L27/08

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US20190051650A1

公开(公告)日：2019-02-14

申请号：US16078675

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Peter G. Tolchinsky ,  Roza Kotlyar ,  Valluri R. Rao

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/16 ,  H01L29/06 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8258 ,  H01L29/66 ,  H01L23/544 ,  H01L23/498

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/49844 ,  H01L23/544 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2223/54493 ,  H04B1/38

Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.

公开(公告)号：US09647636B1

公开(公告)日：2017-05-09

申请号：US15088825

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Telesphor Kamgaing ,  Feras Eid ,  Vijay K. Nair ,  Georgios C. Dogiamis ,  Johanna M. Swan ,  Valluri R. Rao

IPC: G06K19/06 ,  H03H9/30 ,  H03H9/205 ,  H03H9/17 ,  G06K7/10

CPC classification number: G06K7/10297 ,  G06K7/10316 ,  G06K19/0672 ,  G06K19/0675 ,  H03H9/30

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

公开(公告)号：US09166284B2

公开(公告)日：2015-10-20

申请号：US13721245

申请日：2012-12-20

Applicant: INTEL CORPORATION

Inventor： Telesphor Kamgaing ,  Valluri R. Rao ,  Ofir Degani

IPC: H01Q1/38 ,  H01P11/00 ,  H01Q1/22

CPC classification number: H01Q9/045 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01P11/00 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/526 ,  H01Q21/0006 ,  Y10T29/49018

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括形成包括设置在设备的背侧的分立天线的封装结构，其中分立天线包括天线基板，通过天线基板垂直设置的通过天线基板。 垂直设置在器件内的穿通器件衬底通孔经由天线衬底与封装衬底耦合，并且封装衬底与器件的有源侧耦合。

公开(公告)号：US10969574B2

公开(公告)日：2021-04-06

申请号：US16072157

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Thomas L. Sounart ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B26/00 ,  G02B26/08 ,  H01L41/047 ,  H01L41/27 ,  H01L41/314 ,  H01L41/332

Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

公开(公告)号：US10897238B2

公开(公告)日：2021-01-19

申请号：US15088987

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Feras Eid ,  Georgios C. Dogiamis ,  Valluri R. Rao ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Telesphor Kamgaing ,  Vijay K. Nair

IPC: H03H9/54 ,  H03H9/05 ,  H03H9/17 ,  H03H9/15 ,  H03H9/02 ,  H03H9/24

Abstract: Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes.