公开(公告)号：US09422156B2

公开(公告)日：2016-08-23

申请号：US14752718

申请日：2015-06-26

Applicant: InvenSense, Inc.

Inventor： Peter Smeys

IPC: B81C1/00 ,  B81B7/00 ,  B81B7/02

CPC classification number: B81C1/00238 ,  B81B7/02 ,  B81C1/00246 ,  B81C2201/0197 ,  B81C2203/0792

Abstract: A method of providing a CMOS-MEMS structure is disclosed. The method comprises patterning a first top metal on a MEMS actuator substrate and a second top metal on a CMOS substrate. Each of the MEMS actuator substrate and the CMOS substrate include an oxide layer thereon. The method includes etching each of the oxide layers on the MEMS actuator substrate and the base substrate, utilizing a first bonding step to bond the first patterned top metal of the MEMS actuator substrate to the second patterned top metal of the base substrate. Finally the method includes etching an actuator layer into the MEMS actuator substrate and utilizing a second bonding step to bond the MEMS actuator substrate to a MEMS handle substrate.

Abstract translation: 公开了一种提供CMOS-MEMS结构的方法。 该方法包括将MEMS致动器基板上的第一顶部金属和CMOS基板上的第二顶部金属图案化。 MEMS致动器基板和CMOS基板中的每一个在其上包括氧化物层。 该方法包括利用第一结合步骤将MEMS致动器基板的第一图案化顶部金属与基底基板的第二图案化顶部金属结合来蚀刻MEMS致动器基板和基底基板上的每个氧化物层。 最后，该方法包括将致动器层蚀刻到MEMS致动器基板中，并利用第二结合步骤将MEMS致动器基板结合到MEMS手柄基板。

公开(公告)号：US10308503B2

公开(公告)日：2019-06-04

申请号：US15636463

申请日：2017-06-28

Applicant: InvenSense, Inc.

Inventor： Jong Il Shin ,  Peter Smeys ,  Daesung Lee

IPC: B81B7/02 ,  B81C1/00 ,  G01P15/08

Abstract: An apparatus includes a cavity within a substrate. A MEMS structure is within the cavity, wherein the cavity includes the MEMS structure. A trench is connected to the cavity, wherein the trench is not directly opposite the MEMS structure. An oxide layer lines the trench and the cavity. A seal layer seals the trench and traps a predetermined pressure within the cavity and the trench.

公开(公告)号：US09975763B2

公开(公告)日：2018-05-22

申请号：US15457832

申请日：2017-03-13

Applicant: InvenSense, Inc.

Inventor： Jong Il Shin ,  Peter Smeys ,  Jongwoo Shin

IPC: B81C1/00 ,  B81B7/00 ,  B06B1/06

CPC classification number: B81C1/00301 ,  B06B1/06 ,  B81B7/007 ,  B81B2201/0271 ,  B81C1/00238 ,  B81C2203/036 ,  H01L41/113 ,  H01L41/1138 ,  H01L41/31

Abstract: Provided herein is a method including bonding a first oxide layer on a handle substrate to a second oxide layer on a complementary metal oxide semiconductor (“CMOS”), wherein the fusion bonding forms a unified oxide layer including a diaphragm overlying a cavity on the CMOS. The handle substrate is removed leaving the unified oxide layer. A piezoelectric film stack is deposited over the unified oxide layer. Vias are formed in the piezoelectric film stack and the unified oxide layer. An electrical contact layer is deposited, wherein the electrical contact layer electrically connects the piezoelectric film stack to an electrode on the CMOS.

公开(公告)号：US09809450B2

公开(公告)日：2017-11-07

申请号：US14838237

申请日：2015-08-27

Applicant: InvenSense, Inc.

Inventor： Jong Il Shin ,  Peter Smeys ,  Jongwoo Shin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/0006 ,  B81B2207/012 ,  B81C2203/019 ,  B81C2203/036 ,  B81C2203/0792

Abstract: A method and system for forming a MEMS device are disclosed. In a first aspect, the method comprises providing a conductive material over at least a portion of a top metal layer of a base substrate, patterning the conductive material and the at least a portion of the top metal layer, and bonding the conductive material with a device layer of a MEMS substrate via metal silicide formation. In a second aspect, the MEMS device comprises a MEMS substrate, wherein the MEMS substrate includes a handle layer, a device layer, and an insulating layer in between. The MEMS device further comprises a base substrate, wherein the base substrate includes a top metal layer and a conductive material over at least a portion of the top metal layer, wherein the conductive material is bonded with the device layer via metal silicide formation.

公开(公告)号：US20170297909A1

公开(公告)日：2017-10-19

申请号：US15636463

申请日：2017-06-28

Applicant: InvenSense, Inc.

Inventor： Jong Il Shin ,  Peter Smeys ,  Daesung Lee

IPC: B81B7/02 ,  B81C1/00

CPC classification number: B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81C1/00214 ,  B81C1/00293 ,  B81C2203/0118 ,  B81C2203/035 ,  G01P15/0802

Abstract: An apparatus includes a cavity within a substrate. A MEMS structure is within the cavity, wherein the cavity includes the MEMS structure. A trench is connected to the cavity, wherein the trench is not directly opposite the MEMS structure. An oxide layer lines the trench and the cavity. A seal layer seals the trench and traps a predetermined pressure within the cavity and the trench.

公开(公告)号：US09754922B2

公开(公告)日：2017-09-05

申请号：US15040823

申请日：2016-02-10

Applicant: InvenSense, Inc.

Inventor： Peter Smeys ,  Mozafar Maghsoudnia

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16111 ,  H01L2224/16147 ,  H01L2224/16502 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81906 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.