公开(公告)号：US06858502B2

公开(公告)日：2005-02-22

申请号：US09989770

申请日：2001-11-20

申请人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

发明人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

IPC分类号： H01L29/161 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L21/336

CPC分类号： H01L29/7782 ,  H01L29/1025 ,  H01L29/1054

摘要： A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

摘要翻译： 一种用于形成p沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，第一外延Ge层的复合沟道结构和具有较高势垒的第二压缩应变SiGe层 更深的约束量子阱并具有极高的空穴迁移率。 本发明克服了仅具有单个压缩应变SiGe沟道层的p沟道器件的有限空穴迁移率的问题。

公开(公告)号：US06426265B1

公开(公告)日：2002-07-30

申请号：US09774126

申请日：2001-01-30

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：US6059895A

公开(公告)日：2000-05-09

申请号：US311468

申请日：1999-05-13

申请人： Jack Oon Chu ,  Khalid EzzEldin Ismail

发明人： Jack Oon Chu ,  Khalid EzzEldin Ismail

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/12 ,  H01L29/00

CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/2007

摘要： An SOI substrate and method for forming is described incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si and/or S.sub.i O.sub.2 over the strained layers, bonding a second substrate having an insulating layer on its upper surface to the top surface above the strained layers, and removing the first substrate. The invention overcomes the problem of forming strained Si and SiGe layers on insulating substrates.

摘要翻译： 描述SOI衬底和形成方法，其包括在第一衬底上形成Si和/或SiGe的应变层的步骤，在应变层上形成Si和/或SiO 2层，将具有绝缘层的第二衬底 其上表面到应变层上方的顶表面，并且移除第一基底。 本发明克服了在绝缘基板上形成应变Si和SiGe层的问题。

公开(公告)号：US07790538B2

公开(公告)日：2010-09-07

申请号：US12118689

申请日：2008-05-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

摘要翻译： 公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

公开(公告)号：US20090239097A1

公开(公告)日：2009-09-24

申请号：US12051366

申请日：2008-03-19

申请人： Jack Oon Chu ,  Deborah Ann Neumayer

发明人： Jack Oon Chu ,  Deborah Ann Neumayer

IPC分类号： C30B25/18 ,  B32B9/00

CPC分类号： C30B25/18 ,  C30B29/08 ,  Y10S438/933

摘要： A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

摘要翻译： 公开了制备用于外延沉积的III-V族化合物半导体的表面的方法。 III-V族半导体表面在约250℃至约350℃的温度下用硼（B）处理。用于供应B用于表面处理的合适形式是乙硼烷。 B处理可以在与B处理类似的温度下进行外延生长，例如通过IV族半导体。 该方法产生高质量异质结，适用于制造各种器件结构。

公开(公告)号：US07569442B2

公开(公告)日：2009-08-04

申请号：US11158726

申请日：2005-06-22

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/802 ,  Y10S438/933

摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在 晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。 本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变增加迁移率。

公开(公告)号：US07411214B2

公开(公告)日：2008-08-12

申请号：US11067186

申请日：2005-02-26

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

公开(公告)号：US20080132021A1

公开(公告)日：2008-06-05

申请号：US11971392

申请日：2008-01-09

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

公开(公告)号：US20080124860A1

公开(公告)日：2008-05-29

申请号：US12013704

申请日：2008-01-14

申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

公开(公告)号：US07091095B2

公开(公告)日：2006-08-15

申请号：US11053707

申请日：2005-02-08

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/7782 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/1054

摘要： A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.

摘要翻译： 公开了具有拉伸应变SiGe部分和压缩应变SiGe部分的应变结晶层。 应变结晶层以SiGe弛豫缓冲层的顶部外延结合或生长，使得拉伸应变SiGe的Ge浓度低于SiGe松弛缓冲液的Ge浓度，并且压缩应变SiGe的Ge浓度高于 SiGe放松缓冲区的那个。 应变结晶层和松弛缓冲液可以驻留在半绝缘体衬底上或绝缘分隔层的顶部。 在一些实施例中，拉伸SiGe层是纯Si，并且压缩SiGe层是纯Ge。 拉伸应变的SiGe层适用于承载电子传导型器件，压缩应变的SiGe适用于承载空穴传导型器件。 应变结晶层能够接种外延绝缘体或化合物半导体层。