公开(公告)号：US20080073742A1

公开(公告)日：2008-03-27

申请号：US11943277

申请日：2007-11-20

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Stephen Luce ,  Richard Rassell ,  Edmund Sprogis

IPC分类号： H01L31/00 ,  H01L21/98

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20070114622A1

公开(公告)日：2007-05-24

申请号：US11623977

申请日：2007-01-17

申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

IPC分类号： H01L29/82

CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US20070023796A1

公开(公告)日：2007-02-01

申请号：US11161224

申请日：2005-07-27

申请人： James Adkisson ,  John Ellis-Monaghan

发明人： James Adkisson ,  John Ellis-Monaghan

IPC分类号： H01L31/113 ,  H01L31/062

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/1463

摘要： A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.

摘要翻译： 一种新颖的像素传感器单元结构及其制造方法。 像素传感器单元包括第一导电类型的收集阱区域和形成在衬底中的钉扎层。 钉扎层包括第二导电类型的第一杂质区和第二导电类型的第二杂质区。 可以独立地形成第一和第二杂质区域以影响像素传感器单元的多个参数。

公开(公告)号：US20060073689A1

公开(公告)日：2006-04-06

申请号：US10711771

申请日：2004-10-04

申请人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

发明人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

IPC分类号： H01L21/3205

CPC分类号： H01L21/265 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

摘要翻译： 一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

公开(公告)号：US20070287275A1

公开(公告)日：2007-12-13

申请号：US11835745

申请日：2007-08-08

申请人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

发明人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

IPC分类号： H01L21/425

CPC分类号： H01L21/265 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

摘要翻译： 一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：在衬底的顶表面上形成电介质层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，N掺杂物质基本上包含在多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

公开(公告)号：US20060273397A1

公开(公告)日：2006-12-07

申请号：US10908926

申请日：2005-06-01

申请人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

发明人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/045

摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.

摘要翻译： 一种半导体结构及其形成方法。 该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。 第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。 第一和第二晶体管分别形成在第一和第二区域上。 此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。 在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。

公开(公告)号：US20070293025A1

公开(公告)日：2007-12-20

申请号：US11849489

申请日：2007-09-04

申请人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

发明人： James Adkisson ,  Jeffrey Gambino ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L21/04

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/045

摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.

摘要翻译： 半导体结构制造方法。 首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的 并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向 。 接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。 然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

公开(公告)号：US20070013071A1

公开(公告)日：2007-01-18

申请号：US11160461

申请日：2005-06-24

申请人： James Adkisson ,  Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

发明人： James Adkisson ,  Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L22/34 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014

摘要： A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.

摘要翻译： 一种结构及其形成方法。 该结构包括（a）具有顶部衬底表面的衬底; （b）在顶部衬底表面上的集成电路，其中所述集成电路包括电连接到所述集成电路的晶体管的接合焊盘; （c）在顶部基板表面上和集成电路的周边上的保护环; （c）顶部衬底表面上的切口区域，其中所述保护环夹在所述集成电路和所述切口区域之间并物理隔离所述集成电路和所述切口区域，其中所述切口区域包括电连接到所述接合焊盘的探针焊盘，并且其中所述切口区域 适用于通过芯片切割而损坏，而不会损坏集成电路和保护环。

公开(公告)号：US20060128126A1

公开(公告)日：2006-06-15

申请号：US10905043

申请日：2004-12-13

申请人： James Adkisson ,  Mark Jaffe ,  Arthur Johnson ,  Robert Leidy ,  Jeffrey Maling

发明人： James Adkisson ,  Mark Jaffe ,  Arthur Johnson ,  Robert Leidy ,  Jeffrey Maling

IPC分类号： H01L21/425

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.

摘要翻译： 形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成沟槽隔离区域。 该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。 相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。 为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

公开(公告)号：US20060026472A1

公开(公告)日：2006-02-02

申请号：US10710642

申请日：2004-07-27

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Leendert Huisman ,  Mark Jaffe ,  Phillip Nigh ,  Leah Pastel ,  Thomas Sopchak ,  David Sweenor ,  David Vallett

IPC分类号： G06F17/50 ,  G01R31/28

CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。