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公开(公告)号：US07689845B2
公开(公告)日：2010-03-30
申请号：US12245360
申请日：2008-10-03
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译： 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。
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公开(公告)号：US06763484B2
公开(公告)日：2004-07-13
申请号：US09894465
申请日：2001-06-28
申请人： James W. Tschanz , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Siva G. Narendra , Vivek K. De
IPC分类号： G01R3128
CPC分类号： G01R31/318575 , H03K2217/0018
摘要： A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.
摘要翻译： 一种包括使用扫描链的主体偏置的逻辑单元和方法，所述逻辑单元包括包括主体和扫描链的功能单元块，以及耦合到所述扫描链的可变电压源，以从所述扫描链接收控制信号并耦合到所述扫描链 以向身体提供偏置电压，并且该方法包括识别具有身体的功能单元块的优选身体偏置电压; 并且永久地编程耦合到可变电压源的多个控制信号，所述可变电压源向身体提供优选的身体偏置电压。
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公开(公告)号：US06975005B2
公开(公告)日：2005-12-13
申请号：US10689128
申请日：2003-10-20
申请人： Siva G. Narendra , Stephen H. Tang , Zachary Keer , Vivek K. De
发明人： Siva G. Narendra , Stephen H. Tang , Zachary Keer , Vivek K. De
CPC分类号： G05F3/245 , Y10S257/919
摘要： A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.
摘要翻译： 公开了可以在芯片上作为集成电路或系统的一部分或以各种其它形式单独制造的电流基准。 电流参考可以包括具有基本上温度稳定的输出电压的电压源，由基本上温度稳定的输出电压偏置以提供第一输出电流的第一半导体器件，以及提供第二输出电流的第二半导体器件，其中参考电流 被提供大致等于第一和第二输出电流之间的差。
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公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译： 描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。 该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。 一个通道晶体管具有比另一个晶体管更低的阈值电压。 较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。 在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。
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公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译： 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号 控制电路。 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数 ，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。
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26.发明授权公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译： 本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。
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27.发明授权
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译： 在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于 第一组场效应晶体管的阈值电压。 在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。 电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。 当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。 本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。
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公开(公告)号：US07698576B2
公开(公告)日：2010-04-13
申请号：US10955746
申请日：2004-09-30
申请人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译： 公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。
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公开(公告)号：US06734498B2
公开(公告)日：2004-05-11
申请号：US09165483
申请日：1998-10-02
申请人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
发明人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
IPC分类号： H01L2701
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/78606 , H01L29/78645 , H01L29/78648
摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.
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公开(公告)号：US06710642B1
公开(公告)日：2004-03-23
申请号：US10334644
申请日：2002-12-30
申请人： Stephen H. Tang , Siva G. Narendra , Vivek K. De
发明人： Stephen H. Tang , Siva G. Narendra , Vivek K. De
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： According to some embodiments, a bias generation circuit is provided.
摘要翻译： 根据一些实施例，提供偏置产生电路。
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