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74 条记录 (耗时 0.031 秒)

    Integrated circuit defect detection via laser heat and IR thermography
    21.
    发明授权
    Integrated circuit defect detection via laser heat and IR thermography 失效
    通过激光热和红外热像仪进行集成电路缺陷检测

    公开(公告)号：US06387715B1

    公开(公告)日：2002-05-14

    申请号：US09409975

    申请日：1999-09-30

    申请人： Brennan V. Davis ,  Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rosalinda M. Ring

    发明人： Brennan V. Davis ,  Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rosalinda M. Ring

    IPC分类号： H01L2166

    CPC分类号： H01L22/12 ,  G01N25/72

    摘要： Defect detection for post-manufacturing analysis of an integrated circuit die is enhanced via a method and system that use IR thermography to detect defects in circuitry within the die. According to an example embodiment of the present invention, substrate is removed from an integrated circuit die and a target region is exposed. A portion of the target region is heated with an infrared (IR) laser beam, and the die is imaged using IR thermography. The image is compared with a reference image, and damage to the integrated circuit is detected therefrom.

    摘要翻译： 通过使用IR热成像技术检测管芯内电路缺陷的方法和系统，增强了集成电路管芯后制造分析的缺陷检测。 根据本发明的示例性实施例，从集成电路管芯移除衬底并暴露目标区域。 用红外（IR）激光束加热目标区域的一部分，并使用红外热像仪对裸片进行成像。 将图像与参考图像进行比较，并从其检测到集成电路的损坏。

    LED alignment points for semiconductor die
    22.
    发明授权
    LED alignment points for semiconductor die 失效
    LED半导体芯片对准点

    公开(公告)号：US06281028B1

    公开(公告)日：2001-08-28

    申请号：US09409087

    申请日：1999-09-30

    申请人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    发明人： Michael R. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    IPC分类号： H01L2166

    CPC分类号： H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Post-manufacturing analysis of a semiconductor device is enhanced via a method and system that use a light emitting diode (LED) formed in a semiconductor die during its manufacture. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. A conductor is formed that extends from the LED to the back side of the die, and is coupled to a terminal formed on the back side. The LED is activated via the terminal and used to align the die for analysis. By forming a LED within the semiconductor die during its manufacture, post manufacturing analysis is enhanced by the alignment capabilities provided by the readily activated LED.

    摘要翻译： 通过在其制造期间使用形成在半导体管芯中的发光二极管（LED）的方法和系统来增强半导体器件的后制造分析。 根据本发明的示例性实施例，在具有与背面相对的电路侧的半导体管芯内形成LED。 形成从LED延伸到芯片的背面的导体，并且连接到形成在背面的端子。 LED通过端子激活，用于对准芯片进行分析。 通过在其制造期间在半导体管芯内形成LED，通过易激活的LED提供的对准能力来增强后制造分析。

    Substrate removal using thermal analysis
    23.
    发明授权
    Substrate removal using thermal analysis 失效
    使用热分析去除基板

    公开(公告)号：US06277659B1

    公开(公告)日：2001-08-21

    申请号：US09409011

    申请日：1999-09-29

    申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    IPC分类号： H01L2166

    CPC分类号： H01L21/56 ,  B23K26/034 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/50 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A substrate removal approach involves sensing acoustic energy in a semiconductor device as a function of substrate thickness in the device as substrate is being removed. According to an example embodiment of the present invention, a semiconductor chip having substrate at a back side that is opposite circuitry at a circuit side is analyzed. Some or all of the substrate in the back side of the semiconductor chip is removed, and a thinned region having a bottom area is formed. A laser is directed to the bottom area, and a thermal parameter characterizing target circuitry in the device is detected in response to the laser. The detected parameter is used and an indication of the remaining substrate thickness between the bottom area and the circuitry is determined. In response to the indicated thickness, the substrate removal process is controlled, making possible effective control of the substrate removal process.

    摘要翻译： 衬底去除方法包括在衬底被去除的情况下，将器件中的声能作为衬底厚度的函数来检测半导体器件中的声能。 根据本发明的示例性实施例，分析了在背面具有与电路侧相对的电路的衬底的半导体芯片。 去除半导体芯片的背侧中的一部分或全部基板，形成具有底部区域的变薄区域。 激光被引导到底部区域，并且响应于激光器检测表征装置中的目标电路的热参数。 使用检测到的参数，并确定底部区域和电路之间的剩余基板厚度的指示。 响应于所指示的厚度，控制基板去除过程，使得可以有效地控制基板去除过程。

    Semiconductor die analysis via fiber optic communication
    24.
    发明授权
    Semiconductor die analysis via fiber optic communication 失效
    通过光纤通信进行半导体芯片分析

    公开(公告)号：US06850081B1

    公开(公告)日：2005-02-01

    申请号：US10164506

    申请日：2002-06-05

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： G01R31/28 ,  G01R31/319 ,  G01R31/303

    CPC分类号： G01R31/2884 ,  G01R31/31905

    摘要： Semiconductor analysis is improved via the use of fiber optic communications. According to an example embodiment of the present invention, a stimulation device is adapted to stimulate an integrated circuit die, and the die generates a response to the stimulation. An optical signal generator, either incorporated into the die or coupled to the die, detects the response, converts the response to an optical signal and transmits the optical signal. The optical signal is received at a testing arrangement adapted to analyze the die therefrom. The optical signal is used to analyze the die, improving signal quality and the ability to perform high-speed analysis of the die.

    摘要翻译： 通过使用光纤通信改进了半导体分析。 根据本发明的示例性实施例，刺激装置适于刺激集成电路管芯，并且管芯产生对刺激的响应。 将光信号发生器并入芯片或耦合到管芯，检测响应，将响应转换为光信号并发送光信号。 光学信号在适于从其分析模具的测试装置处被接收。 光信号用于分析芯片，提高信号质量和对芯片进行高速分析的能力。

    Atomic force microscopy and signal acquisition via buried insulator
    25.
    发明授权
    Atomic force microscopy and signal acquisition via buried insulator 失效
    原子力显微镜和通过埋层绝缘子的信号采集

    公开(公告)号：US06448096B1

    公开(公告)日：2002-09-10

    申请号：US09864656

    申请日：2001-05-23

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： H01L2100

    CPC分类号： G01Q60/30 ,  G01R31/303 ,  Y10S977/854

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching the insulator layer of the SOI structure. According to an example embodiment of the present invention, a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side is analyzed. An atomic force microscope is scanned across a thinned portion of the back side. The microscope responds to an electrical characteristic, such as a logic state, coupled from circuitry via the insulator portion of the die over which the microscope is being scanned. The response of the microscope to the die is detected and used to detect an electrical characteristic of the die.

    摘要翻译： 通过从背面访问管芯内的电路而不必破坏SOI结构的绝缘体层来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，分析了具有SOI结构的半导体管芯和电路侧的背面相反的电路。 原子力显微镜扫描在背面的薄部分。 显微镜响应诸如逻辑状态的电特性，该电特性通过显微镜正被扫描的裸片的绝缘体部分从电路耦合。 检测显微镜对管芯的响应，并用于检测管芯的电气特性。

    Circuit access and analysis for a SOI flip-chip die
    26.
    发明授权
    Circuit access and analysis for a SOI flip-chip die 失效
    SOI倒装芯片的电路访问和分析

    公开(公告)号：US06448095B1

    公开(公告)日：2002-09-10

    申请号：US09755013

    申请日：2001-01-05

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： H01L2100

    CPC分类号： H01L22/20 ,  G01R31/307

    摘要： Analysis of a flip-chip type IC die having SOI structure is enhanced via analysis and repair of the die that make possible analysis that would typically result in the die being in a state of disrepair. According to an example embodiment of the present invention, a focused ion beam (FIB) is directed at a back side of a flip-chip die having a circuitry in a circuit side opposite a back side, wherein the circuitry including silicon on insulator (SOI) structure. The FIB is used to remove a selected portion of substrate including a portion of the insulator of the SOI structure from the die. The removed substrate exposes an insulator region in the die, and a signal is coupled from circuitry in the die via the exposed insulator region and used to analyze the die. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed. The reconstruction takes place before, during or after the signal is coupled, depending upon the die being analyzed and the type of analysis being performed. In this manner, access for analyzing the die is improved via the ability to couple a signal through the insulator and to repair a portion of the die that has been altered for analysis. Analysis that would otherwise be destructive can be performed and the ability of the die to function after analysis can be maintained.

    摘要翻译： 具有SOI结构的倒装芯片型IC芯片的分析通过分析和修复模具得到增强，这使得可能的分析通常导致模具处于失修状态。 根据本发明的一个示例性实施例，聚焦离子束（FIB）指向倒装芯片的背面，该倒装芯片的背面具有电路侧的电路，其中包括绝缘体上的硅（SOI） ） 结构体。 FIB用于从芯片去除包括SOI结构的绝缘体的一部分的衬底的选定部分。 去除的衬底暴露了管芯中的绝缘体区域，并且信号通过暴露的绝缘体区域从管芯中的电路耦合并用于分析管芯。 材料沉积在暴露的区域中，并且已经去除的模具的选定部分被重建。 重建在信号耦合之前，期间或之后进行，这取决于正在分析的管芯和正在执行的分析的类型。 以这种方式，通过能够通过绝缘体耦合信号并修复已经被改变以用于分析的芯片的一部分的能力来提高用于分析芯片的访问。 否则可以进行破坏性的分析，可以保持分析后的模具功能的能力。

    Optical analysis of integrated circuits
    27.
    发明授权
    Optical analysis of integrated circuits 失效
    集成电路的光学分析

    公开(公告)号：US07019511B1

    公开(公告)日：2006-03-28

    申请号：US09755008

    申请日：2001-01-05

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： G01J5/02 ,  G01R31/00 ,  G01R31/302

    CPC分类号： G01R31/311 ,  G01N21/1717 ,  G01N21/9501 ,  G01N2021/1721 ,  G01R31/304

    摘要： The invention is directed to a system and method for analyzing an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, an optical beam arrangement is adapted to direct a modulated beam at a selected portion of the integrated circuit. The beam is sufficiently modulated to inhibit optical beam intrusion on the structure and operation of the integrated circuit. A reflected optical waveform response is obtained from the SOI selected portion. The inhibition of optical beam intrusion enhances the ability to analyze integrated circuits using an optical beam, making possible the use of analysis methods that otherwise would be difficult or even impossible to use.

    摘要翻译： 本发明涉及用于分析具有绝缘体上硅（SOI）结构的集成电路的系统和方法。 根据本发明的一个示例性实施例，光束装置适于将调制束指向集成电路的选定部分。 光束被充分调制，以阻止光束入射到集成电路的结构和操作上。 从SOI选择部分获得反射光波形响应。 光束入侵的抑制增强了使用光束分析集成电路的能力，使得可能使用否则将难以甚至不可能使用的分析方法。

    IC die analysis via back side lens
    28.
    发明授权
    IC die analysis via back side lens 失效
    通过背面透镜进行IC芯片分析

    公开(公告)号：US06864972B1

    公开(公告)日：2005-03-08

    申请号：US10205766

    申请日：2002-07-26

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M Ring ,  Daniel L. Stone

    IPC分类号： G01N21/956 ,  G01N21/88

    CPC分类号： G01N21/95684

    摘要： The present invention is directed analysis of a flip-chip integrated circuit die having SOI structure that improves the ability to image and analyze selected portions of circuitry in the die. According to an example embodiment of the present invention, a lens is formed in a back side of a flip-chip die and over the insulator portion of SOI structure in the die. Light is directed at the lens and the lens is used to focus the light to target circuitry in the die. A reflection from the circuitry is detected and used to analyze the die, such as by imaging the circuitry in the die and identifying defects therein. The lens formed in the die enhances the ability to focus light to selected circuitry in the die and improves the ability to analyze dies having SOI structure through the insulator.

    摘要翻译： 本发明是具有SOI结构的倒装芯片集成电路管芯的定向分析，其提高了对管芯中的电路的选定部分进行成像和分析的能力。 根据本发明的示例性实施例，透镜形成在倒装芯片的背面中并且在模具中的SOI结构的绝缘体部分上方。 光指向透镜，并且透镜用于将光聚焦到模具中的目标电路。 检测电路的反射并用于分析管芯，例如通过对管芯中的电路进行成像并识别其中的缺陷。 在芯片中形成的透镜增强了将光聚焦到芯片中的所选电路的能力，并提高了通过绝缘体分析具有SOI结构的裸片的能力。

    SOI die analysis of circuitry logic states via coupling through the insulator
    29.
    发明授权
    SOI die analysis of circuitry logic states via coupling through the insulator 有权
    通过绝缘体耦合的电路逻辑状态的SOI裸片分析

    公开(公告)号：US06621281B1

    公开(公告)日：2003-09-16

    申请号：US09755012

    申请日：2001-01-05

    申请人： Jeffrey D. Birdsley ,  Brennan V. Davis ,  Daniel L. Stone ,  Michael R. Bruce ,  Rosalinda M. Ring

    发明人： Jeffrey D. Birdsley ,  Brennan V. Davis ,  Daniel L. Stone ,  Michael R. Bruce ,  Rosalinda M. Ring

    IPC分类号： G01R3102

    CPC分类号： G01R31/307

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.

    摘要翻译： 具有绝缘体上硅（SOI）结构的半导体管芯的分析通过从背面访问管芯内的电路而不破坏SOI结构的薄绝缘体层来增强。 根据示例性实施例，从电路侧具有SOI结构和背面相反电路的半导体管芯的背面去除衬底的一部分。 通过电容耦合装置对管芯内的电路的一部分进行电连接。 电连接用于获得与用于分析的管芯的电路逻辑状态相关的电测量。