公开(公告)号：US20090029547A1

公开(公告)日：2009-01-29

申请号：US11782491

申请日：2007-07-24

申请人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/44

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L27/11521

摘要： A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps.

摘要翻译： 公开了以防止形成异常多晶硅轮廓的方式蚀刻多晶硅材料的方法。 该方法包括提供具有字线的衬底并在所述衬底和字线上沉积多晶硅层。 然后在所述多晶硅层上沉积有机底部抗反射涂层（BARC）层。 执行梯形蚀刻以去除BARC层和多晶硅层的一部分。 梯形蚀刻由一系列蚀刻循环组成，每个循环包括穿透蚀刻和软着色蚀刻。 使用不同的蚀刻剂气体，不同的源和偏压功率，压力，气体流速和时间段进行突破和软着陆蚀刻。 梯形蚀刻导致光滑的多晶硅表面而没有突然的步骤。

公开(公告)号：US20070069328A1

公开(公告)日：2007-03-29

申请号：US11555712

申请日：2006-11-02

申请人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521

摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.

摘要翻译： 提供了一种用于形成分离栅极闪光装置的方法。 在一个实施例中，提供了其上形成介电层的半导体衬底。 形成覆盖在电介质层上的导体层。 掩蔽层沉积在导体层上。 形成覆盖掩模层的光敏层。 对感光层进行图案化和蚀刻以在其中形成开口图案。 掩模层和导体层根据光敏层中的开口图案进行蚀刻。 在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。 蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。 隔离层填充在多个沟槽和掩蔽层上。 掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

公开(公告)号：US20060275984A1

公开(公告)日：2006-12-07

申请号：US11141902

申请日：2005-06-01

申请人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521

摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.

摘要翻译： 提供了一种用于形成分离栅极闪光装置的方法。 在一个实施例中，提供了其上形成介电层的半导体衬底。 形成覆盖在电介质层上的导体层。 掩蔽层沉积在导体层上。 形成覆盖掩模层的光敏层。 对感光层进行图案化和蚀刻以在其中形成开口图案。 掩模层和导体层根据光敏层中的开口图案进行蚀刻。 在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。 蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。 隔离层填充在多个沟槽和掩蔽层上。 掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

公开(公告)号：US20060170029A1

公开(公告)日：2006-08-03

申请号：US11045850

申请日：2005-01-28

申请人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chi-Hsin Lo ,  Shih-Chi Fu ,  Chia-Ta Hsieh ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.

摘要翻译： 一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。 在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。 可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。 然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。 在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。 电介质层被部分蚀刻以形成介电层的多个厚度。 去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

公开(公告)号：US08710560B2

公开(公告)日：2014-04-29

申请号：US11835814

申请日：2007-08-08

申请人： Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC分类号： H01L31/062

CPC分类号： H01L27/14643 ,  H01L24/05 ,  H01L27/14636 ,  H01L2224/05556 ,  H01L2924/12043 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.

摘要翻译： 半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质 所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

公开(公告)号：US08501572B2

公开(公告)日：2013-08-06

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US20110248328A1

公开(公告)日：2011-10-13

申请号：US12757172

申请日：2010-04-09

申请人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底上的第一浮置栅极，浮置栅极具有凹面侧面; 第一个浮动门上的第一个控制门; 与所述第一控制栅极相邻的第一间隔件; 与所述第一浮动栅极的第一侧相邻的第一字线，具有第一距离; 以及与所述第一浮动栅极的第二侧相邻的擦除栅极，其具有小于所述第一距离的第二距离，所述第二侧与所述第一侧相对。

公开(公告)号：US07785966B2

公开(公告)日：2010-08-31

申请号：US11614677

申请日：2006-12-21

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

摘要翻译： 一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。 该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

公开(公告)号：US07700473B2

公开(公告)日：2010-04-20

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧上的尺寸上横向减小以产生底切。

公开(公告)号：US07687794B2

公开(公告)日：2010-03-30

申请号：US11781728

申请日：2007-07-23

申请人： Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/02

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

摘要翻译： PCRAM（相变随机存取存储器）半导体器件中的PCM（相变存储器）单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后，使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。