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    NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION
    1.
    发明申请
    NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION 有权
    新颖的梯子POLY ETCHING返回过程的WORD线POLY PLANARIZATION

    公开(公告)号：US20090029547A1

    公开(公告)日：2009-01-29

    申请号：US11782491

    申请日：2007-07-24

    申请人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

    发明人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L27/11521

    摘要： A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps.

    摘要翻译： 公开了以防止形成异常多晶硅轮廓的方式蚀刻多晶硅材料的方法。 该方法包括提供具有字线的衬底并在所述衬底和字线上沉积多晶硅层。 然后在所述多晶硅层上沉积有机底部抗反射涂层（BARC）层。 执行梯形蚀刻以去除BARC层和多晶硅层的一部分。 梯形蚀刻由一系列蚀刻循环组成，每个循环包括穿透蚀刻和软着色蚀刻。 使用不同的蚀刻剂气体，不同的源和偏压功率，压力，气体流速和时间段进行突破和软着陆蚀刻。 梯形蚀刻导致光滑的多晶硅表面而没有突然的步骤。

    Ladder poly etching back process for word line poly planarization
    2.
    发明授权
    Ladder poly etching back process for word line poly planarization 有权
    用于字线多平面化的梯形多层刻蚀工艺

    公开(公告)号：US07563675B2

    公开(公告)日：2009-07-21

    申请号：US11782491

    申请日：2007-07-24

    申请人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

    发明人： Shih-Chang Liu ,  Yuan-Hung Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L27/11521

    摘要： A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps.

    摘要翻译： 公开了以防止形成异常多晶硅轮廓的方式蚀刻多晶硅材料的方法。 该方法包括提供具有字线的衬底并在所述衬底和字线上沉积多晶硅层。 然后在所述多晶硅层上沉积有机底部抗反射涂层（BARC）层。 执行梯形蚀刻以去除BARC层和多晶硅层的一部分。 梯形蚀刻由一系列蚀刻循环组成，每个循环包括穿透蚀刻和软着色蚀刻。 使用不同的蚀刻剂气体，不同的源和偏压功率，压力，气体流速和时间段进行突破和软着陆蚀刻。 梯形蚀刻导致光滑的多晶硅表面而没有突然的步骤。

    Magnetic memory cells and manufacturing methods
    4.
    发明授权
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US07554145B2

    公开(公告)日：2009-06-30

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L29/76

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

    Spacer for a split gate flash memory cell and a memory cell employing the same
    6.
    发明授权
    Spacer for a split gate flash memory cell and a memory cell employing the same 有权
    分离栅闪存单元的间隔器和采用其的存储单元

    公开(公告)号：US07202130B2

    公开(公告)日：2007-04-10

    申请号：US10775290

    申请日：2004-02-10

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.

    摘要翻译： 间隔物，分裂栅极闪存单元及其相关方法。 在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。 复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。 在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。 复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。 在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

    Magnetic memory cells and manufacturing methods
    8.
    发明申请
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US20070096230A1

    公开(公告)日：2007-05-03

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L43/00 ,  H01L29/82

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。