公开(公告)号：US08420482B2

公开(公告)日：2013-04-16

申请号：US12458732

申请日：2009-07-21

申请人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

发明人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

摘要翻译： 一种非易失性存储器件和一种形成非易失性存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，其中形成隧道绝缘层包括通过以下处理形成多元件绝缘层，所述工艺包括：顺序地提供第一元件源 ，第二元件源和第三元件源，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，并在阻挡绝缘层上形成控制栅电极。

公开(公告)号：US20120267701A1

公开(公告)日：2012-10-25

申请号：US13425584

申请日：2012-03-21

申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也从第一栅极图案分离小于第一和第二厚度之和的距离。

公开(公告)号：US20110215392A1

公开(公告)日：2011-09-08

申请号：US13037502

申请日：2011-03-01

申请人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L23/48 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20110001181A1

公开(公告)日：2011-01-06

申请号：US12829689

申请日：2010-07-02

申请人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

发明人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

摘要翻译： 提供了一种非易失性存储器件。 非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

公开(公告)号：US20100062595A1

公开(公告)日：2010-03-11

申请号：US12458732

申请日：2009-07-21

申请人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

发明人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC分类号： H01L21/336 ,  H01L21/8246

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

摘要翻译： 一种非易失性存储器件和一种形成非易失性存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，其中形成隧道绝缘层包括通过以下处理形成多元件绝缘层，所述工艺包括：顺序地提供第一元件源 ，第二元件源和第三元件源，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，并在阻挡绝缘层上形成控制栅电极。

公开(公告)号：US10685972B2

公开(公告)日：2020-06-16

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

发明人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/115 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US08575682B2

公开(公告)日：2013-11-05

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US08232590B2

公开(公告)日：2012-07-31

申请号：US12829689

申请日：2010-07-02

申请人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

发明人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

摘要翻译： 提供了一种非易失性存储器件。 非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

公开(公告)号：US20120153372A1

公开(公告)日：2012-06-21

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。