公开(公告)号：US08198134B2

公开(公告)日：2012-06-12

申请号：US12836664

申请日：2010-07-15

申请人： Jonathan A. Noquil

发明人： Jonathan A. Noquil

IPC分类号： H01L12/69

CPC分类号： H01L23/49562 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

摘要翻译： 一种集成功率器件模块，包括具有第一和第二间隔衬垫的引线框架，位于第一和第二焊盘之间的一个或多个公共源极 - 漏极引线以及位于第二焊盘外侧的一个或多个漏极引线。 第一和第二晶体管分别与第一和第二焊盘连接，其中第二晶体管的源极电连接到一个或多个公共源极 - 漏极引线。 第一夹子附接到第一晶体管的漏极并电连接到一个或多个公共源极 - 漏极引线。 第二夹子连接到第二晶体管的漏极，并电连接到位于第二焊盘外侧的一个或多个漏极引线。 成型材料封装引线框架，晶体管和夹子以形成模块。

公开(公告)号：US07682877B2

公开(公告)日：2010-03-23

申请号：US12118222

申请日：2008-05-09

申请人： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L21/00

CPC分类号： H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。

公开(公告)号：US20090117690A1

公开(公告)日：2009-05-07

申请号：US12349140

申请日：2009-01-06

申请人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L21/00 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

摘要翻译： 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。

公开(公告)号：US20070267726A1

公开(公告)日：2007-11-22

申请号：US11740475

申请日：2007-04-26

申请人： Jonathan A. Noquil

发明人： Jonathan A. Noquil

IPC分类号： H01L23/02 ,  H01L23/495 ,  H01L23/48

CPC分类号： H01L23/49562 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/36 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

摘要翻译： 一种集成功率器件模块，包括具有第一和第二间隔衬垫的引线框架，位于第一和第二焊盘之间的一个或多个公共源极 - 漏极引线以及位于第二焊盘外部的一个或多个漏极引线。 第一和第二晶体管分别与第一和第二焊盘连接，其中第二晶体管的源极电连接到一个或多个公共源极 - 漏极引线。 第一夹子附接到第一晶体管的漏极并电连接到一个或多个公共源极 - 漏极引线。 第二夹子连接到第二晶体管的漏极，并电连接到位于第二焊盘外侧的一个或多个漏极引线。 成型材料封装引线框架，晶体管和夹子以形成模块。

公开(公告)号：US07256479B2

公开(公告)日：2007-08-14

申请号：US11035918

申请日：2005-01-13

申请人： Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

发明人： Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC分类号： H01L23/495

CPC分类号： H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US07154186B2

公开(公告)日：2006-12-26

申请号：US10803464

申请日：2004-03-18

申请人： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

发明人： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC分类号： H01L23/48

CPC分类号： H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

摘要翻译： 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。