公开(公告)号：US20100052127A1

公开(公告)日：2010-03-04

申请号：US12616943

申请日：2009-11-12

申请人： Seung-Yong Choi ,  Ti Ching Shian ,  Maria Cristina B. Estacio

发明人： Seung-Yong Choi ,  Ti Ching Shian ,  Maria Cristina B. Estacio

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83907 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.

摘要翻译： 一种倒装芯片模制无引线封装（MLP），电导线印制在导电油墨中。 MLP包括一个预成型的引线框，其中电路直接印在其上。 本发明还提供一种制造半导体封装的方法。

公开(公告)号：US20090146284A1

公开(公告)日：2009-06-11

申请号：US12328541

申请日：2008-12-04

申请人： Ji-hwan Kim ,  Seung-yong Choi

发明人： Ji-hwan Kim ,  Seung-yong Choi

IPC分类号： H01L23/02

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/206

摘要： Molded leadless packages having improved stacked structures are disclosed. An exemplary molded leadless package includes a die attaching pad, a plurality of leads spaced apart from the die attaching pad at a periphery region of the die attaching pad, a semiconductor chip on the die attaching pad, a plurality of bonding wires electrically connecting the leads to the semiconductor chip, and a sealing member fixedly enclosing the semiconductor chip and the bonding wires while partly exposing an outer surface of each of the leads. The sealing member fills gaps between the die attaching pad and the leads and includes at least one protrusion protruding downward from the die attaching pad and the leads.

摘要翻译： 公开了具有改进的堆叠结构的成型无引线封装。 示例性的模制无引线封装包括管芯安装焊盘，在管芯安装焊盘的外围区域与管芯安装焊盘间隔开的多个引线，管芯安装焊盘上的半导体芯片，多个电连接引线 半导体芯片，以及固定地包围半导体芯片和接合线的密封构件，同时部分地暴露每个引线的外表面。 密封构件填充管芯附接垫和引线之间的间隙，并且包括从管芯安装垫和引线向下突出的至少一个突起。

公开(公告)号：US09147627B2

公开(公告)日：2015-09-29

申请号：US12616943

申请日：2009-11-12

申请人： Seung-Yong Choi ,  Ti Ching Shian ,  Maria Cristina B. Estacio

发明人： Seung-Yong Choi ,  Ti Ching Shian ,  Maria Cristina B. Estacio

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/83907 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.

摘要翻译： 一种倒装芯片模制无引线封装（MLP），电导线印制在导电油墨中。 MLP包括一个预成型的引线框，其中电路直接印在其上。 本发明还提供一种制造半导体封装的方法。

公开(公告)号：US20100289137A1

公开(公告)日：2010-11-18

申请号：US12845299

申请日：2010-07-28

申请人： Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

发明人： Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

IPC分类号： H01L23/36

CPC分类号： H01L23/3675 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/562 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/0061 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3484 ,  H05K2201/0347 ,  H05K2201/09745 ,  H05K2203/0315 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same.The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

摘要翻译： 提供一种其中半导体封装和散热器彼此结合的散热器封装及其制造方法。 散热器封装包括在其上表面上具有空腔的散热器; 形成在空腔的底面上的金属层; 形成在所述金属层上的焊膏层; 焊膏层上的基板; 以及安装在基板上的引线和半导体芯片。

公开(公告)号：US07786570B2

公开(公告)日：2010-08-31

申请号：US12358758

申请日：2009-01-23

申请人： Joo-Yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

发明人： Joo-Yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/3675 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/562 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/0061 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3484 ,  H05K2201/0347 ,  H05K2201/09745 ,  H05K2203/0315 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same.The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

摘要翻译： 提供一种其中半导体封装和散热器彼此结合的散热器封装及其制造方法。 散热器封装包括在其上表面上具有空腔的散热器; 形成在空腔的底面上的金属层; 形成在所述金属层上的焊膏层; 焊膏层上的基板; 以及安装在基板上的引线和半导体芯片。

公开(公告)号：US07632719B2

公开(公告)日：2009-12-15

申请号：US12350065

申请日：2009-01-07

申请人： Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

发明人： Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

摘要翻译： 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US20090111219A1

公开(公告)日：2009-04-30

申请号：US12350065

申请日：2009-01-07

申请人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

发明人： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

摘要翻译： 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US08604606B2

公开(公告)日：2013-12-10

申请号：US12845299

申请日：2010-07-28

申请人： Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

发明人： Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/3675 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/562 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/0061 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3484 ,  H05K2201/0347 ,  H05K2201/09745 ,  H05K2203/0315 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

摘要翻译： 提供一种其中半导体封装和散热器彼此结合的散热器封装及其制造方法。 散热器封装包括在其上表面上具有空腔的散热器; 形成在空腔的底面上的金属层; 形成在所述金属层上的焊膏层; 焊膏层上的基板; 以及安装在基板上的引线和半导体芯片。

公开(公告)号：US08168475B2

公开(公告)日：2012-05-01

申请号：US12760964

申请日：2010-04-15

申请人： Seung-yong Choi ,  Min-hyo Park

发明人： Seung-yong Choi ,  Min-hyo Park

IPC分类号： H01L21/56 ,  H01L21/60

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/49541 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

摘要翻译： 提供了一种半导体封装，其尺寸小，但包括以等于或大于最小间距的间隔设置的大量端子，以及制造半导体封装的方法。 半导体封装包括具有形成有多个凸块的底表面的半导体芯片，形成在半导体芯片下方的每个包括电连接到至少一个凸块的第一部分的再分布层图案和与第一部分电连接 第一部分，围绕半导体芯片的至少顶表面的封装层，以及形成在再分配层图案下方的图案化绝缘层，并且暴露再分布层图案的第二部分的至少一部分。

公开(公告)号：US20100140786A1

公开(公告)日：2010-06-10

申请号：US12632298

申请日：2009-12-07

申请人： Keun-hyuk LEE ,  Young-sun KO ,  Seung-won LIM ,  Man-kyo JUNG ,  Seung-yong CHOI

发明人： Keun-hyuk LEE ,  Young-sun KO ,  Seung-won LIM ,  Man-kyo JUNG ,  Seung-yong CHOI

IPC分类号： H01L23/498

CPC分类号： H01L23/49531 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/2919 ,  H01L2224/29344 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member.

摘要翻译： 提供了一种包括在直接接合铜（DBC）板上的接合区域的半导体功率模块封装。 半导体功率模块封装包括：一个或多个半导体芯片; 密封所述一个或多个半导体芯片的密封构件; 电连接到所述一个或多个半导体芯片并从所述密封构件露出的多个引线; 以及电连接到所述一个或多个半导体芯片并电连接从所述密封构件露出的外部电路板的外部接合构件。