公开(公告)号：US20230315343A1

公开(公告)日：2023-10-05

申请号：US18331804

申请日：2023-06-08

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Masahiro YOSHIHARA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G06F12/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G11C16/0483 ,  G11C16/10 ,  G06F12/10 ,  G06F3/0679 ,  G06F3/061 ,  G11C16/26 ,  G06F2212/657

Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

公开(公告)号：US20230290390A1

公开(公告)日：2023-09-14

申请号：US18316277

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/1063 ,  G11C7/222 ,  G11C5/025

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20240272833A1

公开(公告)日：2024-08-15

申请号：US18644120

申请日：2024-04-24

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Yuji NAGAI

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F12/0246 ,  G06F12/06 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

公开(公告)号：US20230420054A1

公开(公告)日：2023-12-28

申请号：US18243258

申请日：2023-09-07

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20230066699A1

公开(公告)日：2023-03-02

申请号：US17809114

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Zhao LYU ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Yuji NAGAI ,  Hisashi FUJIKAWA

IPC: G11C7/10 ,  G11C8/06

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

公开(公告)号：US20230039102A1

公开(公告)日：2023-02-09

申请号：US17967909

申请日：2022-10-18

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Yuji NAGAI

IPC: G06F3/06 ,  G06F12/06 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G06F12/02 ,  G11C16/26 ,  G11C7/10

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

公开(公告)号：US20230022082A1

公开(公告)日：2023-01-26

申请号：US17806965

申请日：2022-06-15

Applicant: KIOXIA CORPORATION

Inventor： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/08

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20220317932A1

公开(公告)日：2022-10-06

申请号：US17464791

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Zhao LU ,  Takehisa KUROSAWA ,  Yuji NAGAI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

公开(公告)号：US20220130458A1

公开(公告)日：2022-04-28

申请号：US17647229

申请日：2022-01-06

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.