公开(公告)号：US11657879B2

公开(公告)日：2023-05-23

申请号：US17244246

申请日：2021-04-29

Applicant: Kioxia Corporation

Inventor： Noboru Shibata ,  Hironori Uchikawa ,  Taira Shibuya

IPC: G11C11/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/32 ,  H01L27/115

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459 ,  H01L27/115

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US11972802B2

公开(公告)日：2024-04-30

申请号：US17956648

申请日：2022-09-29

Applicant: Kioxia Corporation

Inventor： Noboru Shibata ,  Hiroshi Sukegawa

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/30

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

公开(公告)号：US11967368B2

公开(公告)日：2024-04-23

申请号：US18295504

申请日：2023-04-04

Applicant: KIOXIA CORPORATION

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56 ,  G06F3/06 ,  G06F11/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C11/5628 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US11915748B2

公开(公告)日：2024-02-27

申请号：US18112507

申请日：2023-02-22

Applicant: Kioxia Corporation

Inventor： Noboru Shibata ,  Yasuyuki Matsuda

IPC: G11C16/10 ,  G11C11/56 ,  G11C11/408 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C11/4085 ,  G11C11/565 ,  G11C16/08 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

公开(公告)号：US11763883B2

公开(公告)日：2023-09-19

申请号：US17568229

申请日：2022-01-04

Applicant: Kioxia Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US11664077B2

公开(公告)日：2023-05-30

申请号：US17344146

申请日：2021-06-10

Applicant: Kioxia Corporation

Inventor： Jun Nakai ,  Noboru Shibata

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/14 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/14 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3445

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

公开(公告)号：US11621039B2

公开(公告)日：2023-04-04

申请号：US17874968

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Noboru Shibata ,  Yasuyuki Matsuda

IPC: G11C16/10 ,  G11C11/56 ,  G11C11/408 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

公开(公告)号：US11309019B2

公开(公告)日：2022-04-19

申请号：US17101431

申请日：2020-11-23

Applicant: KIOXIA CORPORATION

Inventor： Noboru Shibata ,  Tomoharu Tanaka

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12 ,  G11C16/34 ,  G11C16/10

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k

公开(公告)号：US11183243B2

公开(公告)日：2021-11-23

申请号：US16692233

申请日：2019-11-22

Applicant: KIOXIA CORPORATION

Inventor： Weihan Wang ,  Takahiro Shimizu ,  Noboru Shibata

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H03M13/29 ,  G06F11/10 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

公开(公告)号：US11355202B2

公开(公告)日：2022-06-07

申请号：US16832891

申请日：2020-03-27

Applicant: KIOXIA CORPORATION

Inventor： Noboru Shibata ,  Hironori Uchikawa

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/1157 ,  G11C8/14 ,  G11C16/08 ,  G11C16/10 ,  G11C7/08

Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.