公开(公告)号：US20220130754A1

公开(公告)日：2022-04-28

申请号：US17438728

申请日：2019-03-19

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU ,  Tomoya SANUKI ,  Fumitaka ARAI

IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

公开(公告)号：US20210074638A1

公开(公告)日：2021-03-11

申请号：US17015868

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU

IPC: H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.

公开(公告)号：US20250096102A1

公开(公告)日：2025-03-20

申请号：US18814715

申请日：2024-08-26

Applicant: Kioxia Corporation

Inventor： Kazuma HASEGAWA ,  Tomoya SANUKI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor storage device of an embodiment includes a substrate, a seal member, a first memory chip, and a non-signal wiring. The non-signal wiring has a wiring main body. The wiring main body includes a first portion, a second portion, a third portion. The first portion extends in a second direction intersecting the first direction. The second portion is folded back from an end of the first portion to a first side in the second direction. The second portion extends parallel to the first portion. The third portion is folded back from an end of the second portion to a second side in the second direction. The second side is a side opposite to the first side in the second direction. The third portion extends parallel to the second portion.

公开(公告)号：US20250077120A1

公开(公告)日：2025-03-06

申请号：US18805746

申请日：2024-08-15

Applicant: Kioxia Corporation

Inventor： Yoshihiro OHBA ,  Tomoya SANUKI

IPC: G06F3/06

Abstract: According to one embodiment, a controller includes a first interface configured to receive an I/O command specifying first host data from a host, a second interface configured to transmit and receive the first host data to and from a storage, and a computation processing circuit. The computation processing circuit includes an input circuit configured to input the first host data and plural computation parameters, a duplication processing circuit configured to obtain plural first host data by duplicating the first host data, plural first processing circuits configured to execute computation processes using the input plural parameters for the obtained plural first host data, and an output circuit configured to output computation results.

公开(公告)号：US20240428875A1

公开(公告)日：2024-12-26

申请号：US18749161

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Hajime SANO ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Kazuma HASEGAWA

IPC: G11C29/38 ,  G06F13/16

Abstract: A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.

公开(公告)号：US20240099004A1

公开(公告)日：2024-03-21

申请号：US18523494

申请日：2023-11-29

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI

IPC: H10B43/27 ,  G11C5/06 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B43/27 ,  G11C5/063 ,  H01L24/09 ,  H01L25/0657

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

公开(公告)号：US20240014062A1

公开(公告)日：2024-01-11

申请号：US18371669

申请日：2023-09-22

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: H01L21/677

CPC classification number: H01L21/67781 ,  H01L21/67766 ,  H01L21/67769 ,  H01L21/6773 ,  H01L21/68

Abstract: According to one embodiment, when a first case-mounted memory device that includes a first memory device is not connected to a slot of a host apparatus and is stored in a second stocker, the host apparatus causes a second transport device to transport the first case-mounted memory device to the slot, and to connect it thereto. When the first case-mounted memory device is not connected to the slot and is not stored in the second stocker, the host apparatus causes a first transport device to transport the first memory device from a first stocker to a mounter, causes the mounter to mount the first memory device in a case, and causes the second transport device to transport the first case-mounted memory device to the slot and to connect it thereto.

公开(公告)号：US20240014061A1

公开(公告)日：2024-01-11

申请号：US18371536

申请日：2023-09-22

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: H01L21/677 ,  H01L21/67 ,  G01R1/073 ,  G01R1/067 ,  H01L21/66

CPC classification number: H01L21/67769 ,  H01L21/67248 ,  H01L21/67781 ,  H01L21/6773 ,  G01R1/07314 ,  G01R1/06755 ,  H01L22/32

Abstract: According to one embodiment, a cassette housing includes a storage unit, a probe card, and a container. The storage unit stores a semiconductor wafer including a plurality of nonvolatile memory chips. The probe card includes a probe. The probe is configured to be brought into contact with a pad electrode provided on the semiconductor wafer. The container contains heat transfer fluid for lowering or raising temperature of one or both of the probe card and the semiconductor wafer stored in the storage unit.

公开(公告)号：US20220320065A1

公开(公告)日：2022-10-06

申请号：US17847528

申请日：2022-06-23

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Toshio FUJISAWA ,  Hiroshi MAEJIMA ,  Takashi MAEDA

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US20220301625A1

公开(公告)日：2022-09-22

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Yasuhito YOSHIMIZU ,  Keisuke NAKATSUKA ,  Hideto HORII ,  Takashi MAEDA

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/10 ,  G11C16/26 ,  G11C5/02 ,  G11C5/06

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.