利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

194 条记录 (耗时 0.038 秒)

    Semiconductor device
    21.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20080230821A1

    公开(公告)日：2008-09-25

    申请号：US12073615

    申请日：2008-03-07

    申请人： Yutaka Shionoiri

    发明人： Yutaka Shionoiri

    IPC分类号： H01L27/06

    CPC分类号： G06K19/0723 ,  G06K19/0701 ,  G06K19/0715

    摘要： In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.

    摘要翻译： 在能够通过无线通信进行数据通信的半导体装置中，为了抑制交流信号的发送等，半导体装置具备输入无线信号的输入电路，产生恒定电压的第一电路， 作为恒压电路或限幅电路，输入所产生的恒定电压并能够改变半导体器件的阻抗的第二电路以及设置在第一电路和第二电路之间的滤波器。 通过滤波器抑制AC信号的传输，并且防止由于恒定电压的变化而导致的故障或诸如完全不工作的操作缺陷。

    Transmitting and receiving circuit and semiconductor device including the same
    22.
    发明申请
    Transmitting and receiving circuit and semiconductor device including the same 有权
    发射和接收电路和包括其的半导体器件

    公开(公告)号：US20080149738A1

    公开(公告)日：2008-06-26

    申请号：US12003112

    申请日：2007-12-20

    申请人： Masashi Fujita ,  Yutaka Shionoiri

    发明人： Masashi Fujita ,  Yutaka Shionoiri

    IPC分类号： G06K19/06

    CPC分类号： H03F1/56 ,  H03F1/0205 ,  H03F3/245 ,  H03F2200/327

    摘要： An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.

    摘要翻译： 目的在于提供一种在发送和接收电路中可以减少晶体管数量并且可以防止功率转换效率降低的电路配置。 发送和接收电路包括具有N级的倍压整流电路，每个级包括电容器，其中N是正整数。 具有N级的倍压整流电路连接到具有调制功能的电路。 在N级中的任何一级的电容器中，一个电容器的一个电极连接到发送和接收电路的输入端子，并且连接一个电容器的另一个电极的节点连接到具有 解调功能。 由于发送和接收电路可以由更少的晶体管形成，所以可以减小其尺寸。 由于可以防止功率转换效率的降低，所以可以有效地产生电源电位。

    Digital driver and display device
    23.
    发明授权
    Digital driver and display device 失效
    数字驱动器和显示设备

    公开(公告)号：US07375668B2

    公开(公告)日：2008-05-20

    申请号：US11717026

    申请日：2007-03-13

    申请人： Jun Koyama ,  Yutaka Shionoiri

    发明人： Jun Koyama ,  Yutaka Shionoiri

    IPC分类号： H03M1/66

    CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0252 ,  G11C19/00 ,  G11C19/28 ,  H03M9/00

    摘要： A digital driver for display devices which can prevent the delay of digital data and the extended transition time of the digital data, and thus can make good display, and a display device including the above-mentioned digital driver are disclosed. The digital driver according to the present invention is constituted in such a manner that, by successively inputting digital data to a shift register, the digital data are shifted in the shift register, and the resulting output is sent out to latch circuits. Since the digital data are directly inputted to the shift register, the distance over which the data lines are laid around can be shortened, the increase in load due to the laying-around of the data lines which has so far been a problem can be prevented, and the delay of the digital data and the extended transition time of the digital data can be prevented.

    摘要翻译： 一种用于显示装置的数字驱动器，其可以防止数字数据的延迟和数字数据的延长的转换时间，并且因此可以进行良好的显示，并且公开了包括上述数字驱动器的显示装置。 根据本发明的数字驱动器以这样的方式构成，即通过将数字数据连续地输入到移位寄存器，数字数据在移位寄存器中移位，并将所得到的输出发送到锁存电路。 由于数字数据被直接输入到移位寄存器，所以可以缩短数据线的铺设距离，可以防止由于到目前为止存在问题的数据线的铺设而引起的负载的增加 ，并且可以防止数字数据的延迟和数字数据的扩展转换时间。

    Memory and driving method of the same
    25.
    发明授权
    Memory and driving method of the same 有权
    内存和驱动方法相同

    公开(公告)号：US07352604B2

    公开(公告)日：2008-04-01

    申请号：US11607053

    申请日：2006-12-01

    申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC分类号： G11C17/00

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

    摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

    摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

    Circuit having source follower and semiconductor device having the circuit
    28.
    发明授权
    Circuit having source follower and semiconductor device having the circuit 失效

    公开(公告)号：US07081774B2

    公开(公告)日：2006-07-25

    申请号：US10893936

    申请日：2004-07-20

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/082 ,  G11C11/14 ,  G11C11/44

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    Liquid crystal display device
    29.
    发明授权
    Liquid crystal display device 有权

    公开(公告)号：US07053969B2

    公开(公告)日：2006-05-30

    申请号：US10374999

    申请日：2003-02-28

    申请人： Shunpei Yamazaki ,  Shingo Eguchi ,  Yutaka Shionoiri ,  Etsuko Fujimoto

    发明人： Shunpei Yamazaki ,  Shingo Eguchi ,  Yutaka Shionoiri ,  Etsuko Fujimoto

    IPC分类号： G02F1/136

    CPC分类号： G02F1/133555 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/123 ,  H01L27/1255 ,  H01L29/42384

    摘要： It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.

    Method for evaluating semiconductor device
    30.
    发明申请
    Method for evaluating semiconductor device 有权
    半导体器件评估方法

    公开(公告)号：US20050273290A1

    公开(公告)日：2005-12-08

    申请号：US11132434

    申请日：2005-05-19

    申请人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

    发明人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

    IPC分类号： G01R31/317 ,  G01R31/3187 ,  G06F19/00

    CPC分类号： G01R31/3187 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31726

    摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.

    摘要翻译： 本发明提供了一种用于评估预期元素或参数的方法。 此外，本发明提供了一种快速获得更精确结果的评估方法。 根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。