利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

68 条记录 (耗时 0.035 秒)

    Semiconductor device and method for fabricating the same
    22.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07053436B2

    公开(公告)日：2006-05-30

    申请号：US10752668

    申请日：2004-01-08

    申请人： Yoshihisa Nagano ,  Toshie Kutsunai

    发明人： Yoshihisa Nagano ,  Toshie Kutsunai

    IPC分类号： H01L27/108

    CPC分类号： H01L28/55 ,  H01L21/7687 ,  H01L27/10852 ,  H01L28/65

    摘要： A conductive oxygen barrier layer is formed on an interlayer dielectric film and patterned such that it is in contact with the top surface of a contact plug to prevent the diffusion of oxygen into the contact plug from above. The conductive oxygen barrier layer is composed of a lower layer containing a conductive nitride such as TiAlN, and an upper layer containing a conductive oxide such as IrO2. An insulative oxygen barrier layer composed of Al2O3 and having a thickness of approximately 20 nm is formed on the side surfaces of the conductive oxygen barrier layer to prevent the diffusion of oxygen into the contact plug from the sides, such as from the sides of the lower layer of the conductive barrier layer.

    摘要翻译： 导电氧阻隔层形成在层间电介质膜上并被图案化，使得其与接触插塞的顶表面接触以防止氧气从上方扩散到接触塞中。 导电氧阻隔层由包含诸如TiAlN的导电氮化物的下层和包含诸如IrO 2的导电氧化物的上层组成。 在导电氧阻隔层的侧表面上形成厚度约为20nm的由Al 2 O 3 3 N 2构成的绝缘性氧阻隔层，以防止扩散 氧从侧面进入接触塞，例如从导电阻挡层的下层的侧面。

    Semiconductor device and method for fabricating the same
    24.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06849887B2

    公开(公告)日：2005-02-01

    申请号：US09103873

    申请日：1998-06-24

    申请人： Yoshihisa Nagano ,  Toshie Kutsunai ,  Yuji Judai ,  Yasuhiro Uemoto ,  Eiji Fujii

    发明人： Yoshihisa Nagano ,  Toshie Kutsunai ,  Yuji Judai ,  Yasuhiro Uemoto ,  Eiji Fujii

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L29/76

    CPC分类号： H01L27/1085 ,  H01L21/76895 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

    摘要翻译： 半导体器件包括：设置在其上具有集成电路的支撑衬底上并包括下电极，电介质膜和上电极的电容器; 设置为覆盖电容器的第一层间绝缘膜; 选择性地设置在所述第一层间绝缘膜上并通过形成在所述第一层间绝缘膜中的第一接触孔与所述集成电路和所述电容器电连接的第一互连; 由臭氧TEOS形成的第二层间绝缘膜，并设置为覆盖第一互连; 选择性地设置在第二层间绝缘膜上并通过形成在第二层间绝缘膜中的第二接触孔电连接到第一互连的第二互连; 以及设置成覆盖第二互连的钝化层。

    Method of manufacturing semiconductor devices
    25.
    发明授权
    Method of manufacturing semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US5599424A

    公开(公告)日：1997-02-04

    申请号：US571732

    申请日：1995-12-13

    申请人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    发明人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/00

    CPC分类号： H01L28/40

    摘要： On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

    摘要翻译： 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

    Method of manufacturing a capacitor having metal electrodes
    28.
    发明授权
    Method of manufacturing a capacitor having metal electrodes 失效
    制造具有金属电极的电容器的方法

    公开(公告)号：US5527729A

    公开(公告)日：1996-06-18

    申请号：US412563

    申请日：1995-03-29

    申请人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    发明人： Shoji Matsumoto ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Yasufumi Izutsu

    IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L28/40

    摘要： On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

    摘要翻译： 在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。 一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由 半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。 使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。