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公开(公告)号：US07000162B2
公开(公告)日：2006-02-14
申请号：US09682233
申请日：2001-08-08
CPC分类号： G01R31/2856 , G01R31/2879 , H01L22/34
摘要： Disclosed is an integrated circuit device, comprising: a first power rail for supplying power to first latch and a circuit during a first clock phase; a second power rail for supplying power to a second latch during a second clock phase; and the circuit coupled between an output of the first latch and an input of the second latch.
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22.发明授权Body-contacted and double gate-contacted differential logic circuit and method of operation 有权身体接触和双门接触差分逻辑电路及其操作方法公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。
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公开(公告)号：US06433587B1
公开(公告)日：2002-08-13
申请号：US09528207
申请日：2000-03-17
IPC分类号： H03K19096
CPC分类号： H03K19/00361 , H03K19/096
摘要： A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.
摘要翻译： 用于维持在动态CMOS电路中实现的晶体管的阈值电压的电路。 多个晶体管具有连接在动态CMOS电路中的晶体管的主体触点之间的源极漏极连接以及恒定的电压电位。 当在预充电阶段中操作动态CMOS电路时，每个CMOS电路晶体管的主体保持在恒定的电压电位。 在评估阶段，允许身体电位浮动到其预充电状态。 在预充电阶段期间建立的初始参考电平电压将晶体管栅极 - 源极阈值电压保持在恒定值，消除伴随身体电位变化的双极效应和历史效应。
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公开(公告)号：US06433372B1
公开(公告)日：2002-08-13
申请号：US09527863
申请日：2000-03-17
申请人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
发明人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H01L2972
CPC分类号： H01L29/66484
摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.
摘要翻译： 具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。 通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层 绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。
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公开(公告)号：US07757137B2
公开(公告)日：2010-07-13
申请号：US11691856
申请日：2007-03-27
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575
摘要： The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.
摘要翻译： 本发明包括用于LSSD或GSD IC操作的新型扫描链结构。 扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2） 功率模式操作，其中锁存器的长扫描链内的每个触发器包括布置用于正常模式操作的数据输入，数据输出，时钟输入，扫描输入和扫描输出输出。 缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫描输入端之间用于扫描链中的下一个锁存器，缓冲电路包括一个 控制元件，其控制第一触发器（L1）的扫描模式或低功率泄漏模式的操作。 在从低功率泄漏模式退出时，第一触发器（L1）被设置为数据输出值，该值是在正常模式操作期间初始化时被设置为相同的值。 开关仅在一个时钟周期内发生。
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公开(公告)号：US07701035B2
公开(公告)日：2010-04-20
申请号：US11164640
申请日：2005-11-30
申请人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
发明人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
摘要翻译： 本发明涉及一种用于大功率应用的激光熔丝结构。 具体地，本发明的激光熔丝结构包括第一和第二导电支撑元件（12a，12b），至少一个导电熔丝（14），第一和第二连接元件（20a，20b）以及第一和第二金属线 （22a，22b）。 导电支撑元件（12a，12b），导电熔丝（14）和金属线（22a，22b）位于第一金属层（3）处，而连接元件（20a，20b）位于 第二不同的金属层（4），并且通过在第一和第二金属层之间延伸的导电通孔叠层（18a，18b，23a，23b）连接到导电支撑元件（12a，12b）和金属线（22a，22b） 第二金属含量（3,4）。
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公开(公告)号：US07602635B2
公开(公告)日：2009-10-13
申请号：US11947092
申请日：2007-11-29
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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28.发明授权公开(公告)号：US07129545B2
公开(公告)日：2006-10-31
申请号：US10906563
申请日：2005-02-24
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.
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公开(公告)号：US06455336B1
公开(公告)日：2002-09-24
申请号：US09682381
申请日：2001-08-27
IPC分类号： H01L2166
CPC分类号： G01R31/2879 , G01R31/2856
摘要： A design and burn-in technique that effectively reduces power consumption during burn-in for devices with high power consumption as a result of shrinking voltages, high instantaneous current, subthreshold leakage and high currents at stress conditions. Three methods of reducing power consumption during burn-in are disclosed in detail: (1) completely separate power grids, (2) isolated grids during burn-in, and (3) isolated grids for MTCMOS used during burn-in. Each technique provides a method of segmenting the power supply of a chip and controlling which segment of the chip is stressed based on which segment is ‘powered on’. Those segments not being stressed are ‘shutoff’ so as to reduce power consumption.
摘要翻译： 一种设计和老化技术，可以有效降低由于电压缩减，高瞬时电流，亚阈值泄漏和应力条件下的高电流而导致高功耗器件老化过程中的功耗。 详细介绍了三种降低老化过程中功耗的方法：（1）完全分离电网，（2）老化期间的隔离栅格，（3）老化过程中使用的MTCMOS隔离网格。 每种技术提供了一种分割芯片的电源的方法，并且基于哪个部分被“通电”来控制芯片的哪个片段被应力，那些不受应力的片段是“关闭”，以便降低功耗。
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公开(公告)号：US07450413B2
公开(公告)日：2008-11-11
申请号：US11463917
申请日：2006-08-11
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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