公开(公告)号：US5747847A

公开(公告)日：1998-05-05

申请号：US708269

申请日：1996-09-06

申请人： Hiroyuki Morinaka ,  Kimio Ueda ,  Koichiro Mashiko

发明人： Hiroyuki Morinaka ,  Kimio Ueda ,  Koichiro Mashiko

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L29/66651 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/4908 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.

摘要翻译： 具有能够防止晶体管的击穿电压劣化而不损害集成度的SOI结构的半导体集成电路器件，以及半导体集成电路器件的制造方法。 在P型硅层的整个表面上不形成嵌入的氧化物膜，但在位于栅电极下方的区域中具有开口。 填充开口以形成穿透P层。 因此，SOI层通过穿透P层与P型硅层电连接。 栅电极的平面位置和形状与穿透层P的平面位置和形状一致。

公开(公告)号：US5633524A

公开(公告)日：1997-05-27

申请号：US580609

申请日：1995-12-29

申请人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

发明人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

IPC分类号： H01L21/82 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L27/10 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/118 ,  H01L27/11807 ,  H01L27/1203

摘要： In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).

摘要翻译： 为了提高耐压并实现具有较大栅极宽度的栅阵列SOI半导体集成电路器件，在通过重复布置基本单元（BC）形成的区域的每个端部上设置由端单元（49）组成的区域，所述基本单元（BC） 的两个晶体管区域（32,33）在第一方向上并且同时对称地布置在第二方向上被折叠。 PMOS晶体管（42）的沟道区域的两端在第二方向上被拉出以提供刚好在场屏蔽栅极（FG）下面的P型半导体层，并且该半导体层也沿第一方向 与端电池（49）的P型半导体层连接。 将第一源极电位施加到与一个P型半导体层接合的区域（PBD）。 另一方面，与通过场氧化膜（FO）相邻的NMOS晶体管（41）也类似地设置N型半导体层，使得该N型半导体层也与 端单元（49）。 第二源电位被应用于区域（NBD）。

公开(公告)号：US5541529A

公开(公告)日：1996-07-30

申请号：US450757

申请日：1995-05-25

申请人： Koichiro Mashiko ,  Hiroaki Suzuki

发明人： Koichiro Mashiko ,  Hiroaki Suzuki

IPC分类号： G11C11/413 ,  H03K19/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17792 ,  H03K19/0013 ,  H03K19/1736 ,  H03K19/17704

摘要： A field programmable gate array includes a logic blocks, switching elements for establishing a signal propagation path, and memory cells provided corresponding to the switching elements for storing data determining on and off states of corresponding switching elements. In this gate array, a supply voltage fed to a power input terminal is transmitted to power supply nodes of logic circuit blocks. A booster circuit boosts the supply voltage fed to the power input terminal and feeds the boosted voltage to power supply nodes of memory cells for programming a signal propagation path. A high-level signal potential of each memory cell is fed to the gate of an n-channel MOS transistor which functions as the switching element. The switching elements are disposed on signal lines and serve to interconnect the signal lines selectively to establish a signal propagation path. The current supply capability of the MOS transistors is enhanced to realize faster propagation of the signal, and any harmful influence of the threshold voltage exerted on the signal amplitude loss can be suppressed by a rise of the gate potential in each MOS transistor.

摘要翻译： 现场可编程门阵列包括逻辑块，用于建立信号传播路径的开关元件，以及与开关元件对应地提供的存储单元，用于存储确定相应开关元件的导通和截止状态的数据。 在该门阵列中，馈送到电力输入端的电源电压被发送到逻辑电路块的电源节点。 升压电路提高馈送到电源输入端的电源电压，并将升压的电压馈送到存储器单元的电源节点，以编程信号传播路径。 每个存储单元的高电平信号电位被馈送到用作开关元件的n沟道MOS晶体管的栅极。 开关元件设置在信号线上并用于选择性地互连信号线以建立信号传播路径。 提高MOS晶体管的电流供应能力以实现信号的更快的传播，并且通过每个MOS晶体管中的栅极电位的上升可以抑制施加在信号幅度损失上的阈值电压的任何有害影响。

公开(公告)号：US5274746A

公开(公告)日：1993-12-28

申请号：US605708

申请日：1990-10-30

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  H01L27/10 ,  G06F7/00 ,  G11C11/40 ,  G11C11/54

CPC分类号： G06N3/063

摘要： A neural network device includes internal data input lines, internal data output lines, coupling elements provided at the connections of the internal data input lines and the internal data output lines, word lines each for selecting one row of coupling elements. The coupling elements couple, with specific programmable coupling strengths, the associated internal data input lines to the associated internal data output lines. In a program mode, the internal data output lines serve as signal lines for transmitting the coupling strength information. Each of the coupling elements includes memories constituted of cross-coupled inverters for storing the coupling strength information, first switching transistors responsive to signal potentials on associated word lines for connecting the memories to associated internal data output lines, second switching elements responsive to signal potentials on associated internal data input lines for transmitting the storage information in the memories to the associated internal data output lines. Each of the internal data output lines has a pair of first and second internal data output lines.

摘要翻译： 神经网络装置包括内部数据输入线，内部数据输出线，在内部数据输入线和内部数据输出线的连接处提供的耦合元件，用于选择一行耦合元件的字线。 耦合元件具有特定的可编程耦合强度，将相关联的内部数据输入线耦合到相关联的内部数据输出线。 在程序模式中，内部数据输出线用作发送耦合强度信息的信号线。 每个耦合元件包括由用于存储耦合强度信息的交叉耦合逆变器构成的存储器，响应于相关联的字线上的信号电位的第一开关晶体管，用于将存储器连接到相关联的内部数据输出线，第二开关元件响应于信号电位 用于将存储器中的存储信息发送到相关联的内部数据输出线的相关联的内部数据输入线。 每个内部数据输出线具有一对第一和第二内部数据输出线。

公开(公告)号：US4896197A

公开(公告)日：1990-01-23

申请号：US132645

申请日：1987-12-08

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10835

摘要： A first impurity region is formed on the inner surface of a trench formed on the major surface of a semiconductor substrate. The trench is filled with a vertical portion of a first electric conductor having a reversed L-shaped cross section through an insulating film. A first transistor having a first impurity region serving as a source/drain region is formed on the semiconductor substrate. A second impurity region serving as a source/drain region of a second transistor is formed on the major surface of the semiconductor substrate and spaced from the trench. A second electric conductor having a reversed L-shaped cross section for connecting the vertical portion to the second impurity region is formed, and a horizontal portion of the second electric conductor is formed to be stacked on a horizontal portion of the first electric conductor with an insulating film formed therebetween.

摘要翻译： 第一杂质区域形成在形成在半导体衬底的主表面上的沟槽的内表面上。 沟槽填充有通过绝缘膜具有反向L形横截面的第一导电体的垂直部分。 在半导体衬底上形成具有用作源/漏区的第一杂质区的第一晶体管。 用作第二晶体管的源极/漏极区的第二杂质区域形成在半导体衬底的主表面上并与沟槽间隔开。 形成具有用于将垂直部分连接到第二杂质区域的具有反向的L形横截面的第二导电体，并且第二导电体的水平部分形成为堆叠在第一导电体的水平部分上， 在它们之间形成绝缘膜。

公开(公告)号：US07898449B2

公开(公告)日：2011-03-01

申请号：US12562664

申请日：2009-09-18

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。