公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

申请人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12 ,  H03F3/45

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20090278716A1

公开(公告)日：2009-11-12

申请号：US12436289

申请日：2009-05-06

申请人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

发明人： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US07612700B2

公开(公告)日：2009-11-03

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US5959469A

公开(公告)日：1999-09-28

申请号：US934558

申请日：1997-09-22

申请人： Akira Kurauchi ,  Akira Yukawa

发明人： Akira Kurauchi ,  Akira Yukawa

IPC分类号： H03M1/34 ,  H03K5/08 ,  H03K5/24 ,  H03K5/153 ,  G06G7/64

CPC分类号： H03K5/249

摘要： A chopper comparator for comparing an analog input signal voltage and a comparative reference voltage comprises the following elements. First and second input terminals are provided for receiving the analog input signal voltage and the comparative reference voltage respectively. A first capacitor is provided with a first input side terminal connected through a first switch to the first input terminal. A second capacitor is provided with a second input side terminal connected through a second switch to the second input terminal. A data latch circuit is provided and is connected to first and second output terminals of the first and second capacitors. A third switch is provided between the first and second input side terminals of the first and second capacitors, wherein after the first and second switches have turned OFF to discontinue applications of the analog input signal voltage and the comparative reference voltage to the first and second capacitors respectively, the third switch turns ON to form a short circuit between the first and second input side terminals of the first and second capacitors.

摘要翻译： 用于比较模拟输入信号电压和比较参考电压的斩波比较器包括以下元件。 第一和第二输入端分别用于接收模拟输入信号电压和比较参考电压。 第一电容器设置有通过第一开关连接到第一输入端子的第一输入侧端子。 第二电容器设置有通过第二开关连接到第二输入端子的第二输入侧端子。 提供数据锁存电路并连接到第一和第二电容器的第一和第二输出端。 在第一和第二电容器的第一和第二输入侧端子之间提供第三开关，其中在第一和第二开关已经断开以中断对第一和第二电容器的模拟输入信号电压和比较参考电压的应用之后 第三开关分别导通，在第一和第二电容器的第一和第二输入端之间形成短路。

公开(公告)号：US20090146854A1

公开(公告)日：2009-06-11

申请号：US12139754

申请日：2008-06-16

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara

IPC分类号： H03M1/12

CPC分类号： H03M1/002 ,  H03M1/0695 ,  H03M1/164 ,  H03M1/361 ,  H03M1/442

摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

摘要翻译： 在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号， 用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。 预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于 输入信号到每个A / D转换器电路部分。

公开(公告)号：US07898449B2

公开(公告)日：2011-03-01

申请号：US12562664

申请日：2009-09-18

申请人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US07683819B2

公开(公告)日：2010-03-23

申请号：US12071125

申请日：2008-02-15

申请人： Akira Kurauchi

发明人： Akira Kurauchi

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/0607 ,  H03M1/0695 ,  H03M1/44

摘要： Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.

摘要翻译： 公开了一种流水线ADC，其中在构成第n和第（n + 1）级的本地A / D转换器的电路块之间共享运算放大器，第n级的采样电容器被分成多个采样电容器，以及 采用在第n级分割的多个采样电容器中的一些作为第（n + 1）级的采样电容器。

公开(公告)号：US20080198057A1

公开(公告)日：2008-08-21

申请号：US12071125

申请日：2008-02-15

申请人： Akira Kurauchi

发明人： Akira Kurauchi

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/0607 ,  H03M1/0695 ,  H03M1/44

摘要： Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.

摘要翻译： 公开了一种流水线ADC，其中在构成第n和第（n + 1）级的本地A / D转换器的电路块之间共享运算放大器，第n级的采样电容器被分成多个采样电容器，以及 采用在第n级分割的多个采样电容器中的一些作为第（n + 1）级的采样电容器。