公开(公告)号：US20120025394A1

公开(公告)日：2012-02-02

申请号：US13191818

申请日：2011-07-27

申请人： Hiroshige Hirano ,  Yukitoshi Ota ,  Yutaka Itoh

发明人： Hiroshige Hirano ,  Yukitoshi Ota ,  Yutaka Itoh

IPC分类号： H01L23/48

CPC分类号： H01L21/76807 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.

摘要翻译： 半导体器件包括：形成在衬底上的第一绝缘膜; 嵌入在所述第一绝缘膜中的焊盘; 以及第二绝缘膜，其形成在所述第一绝缘膜上并具有暴露所述焊盘的至少一部分的开口。 焊盘包括多个焊盘互连，并且提供互连链路以电连接多个焊盘互连中的相邻互连。 焊盘互连的宽度小于焊盘互连的高度，并且大于互连链路的宽度。

公开(公告)号：US08710667B2

公开(公告)日：2014-04-29

申请号：US13289683

申请日：2011-11-04

申请人： Hiroshige Hirano ,  Yukitoshi Ota

发明人： Hiroshige Hirano ,  Yukitoshi Ota

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.

摘要翻译： 半导体器件包括设置在第一互连层上方或下方的第一互连层和第二互连层。 第一互连层包括多个第一互连块，并且在每个第一互连块中，第一互连具有第一电位，并且在至少两个或更多个方向上延伸，并且第二互连具有第二电位，并且延伸 在至少两个或更多个方向。 第二互连层包括第三互连，其将一对相邻的第一互连块中的一个的第一互连与该对相邻的第一互连块中的另一个的第一互连电连接，以及将第二互连电连接的第四互连 所述一对相邻的第一互连块中的一个和所述一对相邻的第一互连块中的另一个的所述第二互连。

公开(公告)号：USRE41879E1

公开(公告)日：2010-10-26

申请号：US12155392

申请日：2008-06-03

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

IPC分类号： G11C16/06

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

公开(公告)号：US20060285378A1

公开(公告)日：2006-12-21

申请号：US11356213

申请日：2006-02-17

申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

摘要翻译： 为了省略存储单元的存储节点和单元板极线之间的复位晶体管，单元板线固定为基本上等于接地电位的电位，并且用正和负电压驱动位线。

公开(公告)号：US07136313B2

公开(公告)日：2006-11-14

申请号：US11121939

申请日：2005-05-05

申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

公开(公告)号：US20050258886A1

公开(公告)日：2005-11-24

申请号：US11132272

申请日：2005-05-19

申请人： Hiroshige Hirano

发明人： Hiroshige Hirano

IPC分类号： H03K19/0185 ,  H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03L5/00

CPC分类号： H03K3/012 ,  H03K3/356113 ,  H03K3/356165 ,  H03K17/102

摘要： A voltage level conversion circuit 101 is provided with a level converter 101a for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit 30 for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits 21a and 21b constituting the level converter 101a are input to only high breakdown voltage transistors Qhn1 and Qhn2 in the level converter 101a while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors Qlp1 and Qlp2, and further, only the input signal level-converted by the level converter 101a is input to the NOT circuit 30.

摘要翻译： 电压电平转换电路101具有用于将VDD 1系统输入信号转换为VDD 2系统信号的电平转换器101a和用于反相电平转换输入信号并输出​​反相信号的NOT电路30， 构成电平转换器101a的VDD1系统NOT电路21a和21b的输出仅输入到电平转换器101a中的高击穿电压晶体管Qhn 1和Qhn 2，而具有对应于低功率的逻辑电压电平的信号 电源电压VDD 2被输入到低击穿电压晶体管Qlp1和Q1p2，此外，仅电平转换器101a的电平转换的输入信号被输入到NOT电路30。

公开(公告)号：US06353550B1

公开(公告)日：2002-03-05

申请号：US09661370

申请日：2000-09-13

申请人： Hiroshige Hirano

发明人： Hiroshige Hirano

IPC分类号： G11C1112

CPC分类号： G11C11/22

摘要： The ferroelectric memory device includes a plurality of memory cells arranged in a matrix at crossings of a plurality of word lines and a plurality of bit lines. Each memory cell includes at least one ferroelectric capacitor composed of a ferroelectric film and first and second electrodes sandwiching the ferroelectric film, a memory cell transistor interposed between the bit line and the first electrode of the ferroelectric capacitor, a cell plate line connected to the second electrode of the ferroelectric capacitor, a reset voltage supply line for supplying a voltage of a potential substantially identical to the potential at the cell plate line, a reset transistor interposed between the reset voltage supply line and the first electrode of the ferroelectric capacitor, and a reset control signal line for controlling ON/OFF of the reset transistor.

摘要翻译： 铁电存储器件包括在多个字线和多个位线的交叉处以矩阵布置的多个存储单元。 每个存储单元包括至少一个由铁电体膜构成的铁电电容器和夹持铁电体膜的第一和第二电极，插入在位线和强电介质电容器的第一电极之间的存储单元晶体管，连接到第二 所述强电介质电容器的电极，用于提供与所述电池板线的电位基本相同的电位的电压的复位电压供给线，配置在所述复位电压供给线与所述强电介质电容的第一电极之间的复位晶体管， 用于控制复位晶体管的导通/截止的复位控制信号线。

公开(公告)号：US06246624B1

公开(公告)日：2001-06-12

申请号：US09198726

申请日：1998-11-24

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： G11C700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

摘要翻译： 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US5953277A

公开(公告)日：1999-09-14

申请号：US037864

申请日：1998-03-10

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 用于向信号线21和22提供电荷的充电提供电路; 连接充电电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两条信号线21和22连接在一起的第二连接电路25，在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容的平均值之后，两条信号线断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5920509A

公开(公告)日：1999-07-06

申请号：US888307

申请日：1997-07-03

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

摘要翻译： 通过将全部组反转控制栅极设置为逻辑电压“H”，存储单元阵列块的所有位线上的存储单元连接到反向电压供应电路，从而执行组反转操作。 当组反转控制门中的一个被设置为逻辑电压“H”时，具有偶数或奇数个存储单元阵列块的位线上的存储单元连接到反向电压供应电路，使得部分组 执行反转操作。 当列选择门之一被设置为逻辑电压“H”时，所选择的位线连接到反向电压供应电路。 因此，执行连接到所选位线的存储单元的线路反向操作。 因此，可以实现完全控制存储单元的截止电流的高速反转操作，并且可以通过改变用于执行反转操作的操作单元来实现低电压操作。