公开(公告)号：US20080316787A1

公开(公告)日：2008-12-25

申请号：US12199684

申请日：2008-08-27

申请人： Shozo KAWABATA ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

发明人： Shozo KAWABATA ,  Kenji Shibata ,  Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C15/00 ,  G11C8/00

CPC分类号： G11C15/00

摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

公开(公告)号：US20060226529A1

公开(公告)日：2006-10-12

申请号：US11448863

申请日：2006-06-08

申请人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

发明人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

IPC分类号： H01L23/02

CPC分类号： H01L22/22 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/8513 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

公开(公告)号：US07106651B2

公开(公告)日：2006-09-12

申请号：US11066484

申请日：2005-02-28

申请人： Kenji Nagai ,  Satoru Kawamoto

发明人： Kenji Nagai ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/103 ,  G11C8/12 ,  G11C11/413 ,  G11C2207/2245

摘要： A semiconductor memory device is arranged so that its circuit area is made smaller and the stored data may be constantly outputted at fast speed. The semiconductor memory device includes a memory cell array and an auxiliary cell array concatenated with word lines on the increasing side of bit-line addresses in the memory cell array. The auxiliary cell array stores data of memory cells in the range from a first bit-line address on a next word-line address to a bit-line address located apart by a predetermined number of bits. A Y-address driver is also included in the semiconductor memory device. The Y-address driver reads data from the auxiliary cell array following the last bit-line address if the read of data pieces at a time ranges from the last bit-line address to the first bit-line address on the next word-line address in the memory cell array.

摘要翻译： 半导体存储器件被布置成使其电路面积更小，并且可以以快速的速度恒定地输出存储的数据。 半导体存储器件包括存储单元阵列和与存储单元阵列中的位线地址的增加侧的字线连接的辅助单元阵列。 辅助单元阵列将存储单元的数据存储在从下一个字线地址上的第一位线地址到分隔预定位数的位线地址的范围内。 Y地址驱动器也包括在半导体存储器件中。 Y地址驱动器从最后一个位线地址之后的辅助单元阵列读取数据，如果数据段的读取时间范围从下一个字线地址上的最后位线地址到第一个位线地址 在存储单元阵列中。

公开(公告)号：US07081776B2

公开(公告)日：2006-07-25

申请号：US11057143

申请日：2005-02-15

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22 ,  H03K5/153

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

摘要翻译： 一种电压检测电路，用于在抑制由晶体管的漏电流引起的电压波动的同时精确地检测电压。 电压检测电路包括第一和第二电容器，第一和第二晶体管，比较器和控制电路。 电容器串联连接以产生对应于电容器的高电压的分压。 当晶体管被激活时，第一电容器和第二电容器之间的节点处的电位被复位为接地电位。 当节点处的电位达到预定电位时，第一晶体管失活，然后第二晶体管失活。

公开(公告)号：US20060152291A1

公开(公告)日：2006-07-13

申请号：US11372146

申请日：2006-03-10

申请人： Yasushige Ogawa ,  Satoru Kawamoto

发明人： Yasushige Ogawa ,  Satoru Kawamoto

IPC分类号： H03L7/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

公开(公告)号：US20060044919A1

公开(公告)日：2006-03-02

申请号：US11215889

申请日：2005-08-30

申请人： Hideho Taoka ,  Yoshihiro Suzumura ,  Kanji Hirano ,  Satoru Kawamoto

发明人： Hideho Taoka ,  Yoshihiro Suzumura ,  Kanji Hirano ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C16/16 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468 ,  G11C2216/18

摘要： During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.

摘要翻译： 在擦除顺序期间，在预编程操作（S1）之后，执行擦除操作（S 3）和APDE操作（S 5）并通过APDE验证操作（S 6：P）进行确认并通过擦除确认 （S 7：P）完成时，在多个存储单元的软编程操作（S10）之前执行步骤A. 连续执行虚拟存储器单元编程操作（S 8），直到通过虚拟存储器单元程序验证操作确认完成编程操作（S 9）。 通过对虚拟存储单元执行程序操作，通过位线将与程序操作类似的电压应力施加于过擦除状态的存储单元。 因此，过擦除状态被降低，从而降低列泄漏电流。 可以防止在软程序验证操作期间的错误识别（S11），并且可以避免过多的软编程。

公开(公告)号：US06717868B2

公开(公告)日：2004-04-06

申请号：US10260286

申请日：2002-10-01

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C2207/002 ,  G11C2207/2281

摘要： There is provided an inventive semiconductor memory device and control method thereof capable of preventing shift operation to deactivated state and data access due to transition of address signals from occurring concurrently without accompanying delay of access time, thereby to prevent data-holding characteristic of memory cell from deteriorating. A column selecting circuit 16 is deactivated based on an input signal EXBn outputted to a glitch canceller 20 prior to precharge signal PRE so as to prevent selection of a column selecting signal CLn and deactivation of a word line WL from occurring concurrently. This manner substitutes for taking delay time &tgr;D that is to be added to signals CAGn from which glitch noises due to transition of address CAn are eliminated. Thereby, address-access time, namely, from transition of address CAn till selection of a column selecting signal CLn, is kept in the shortest access time tAAX0 and the column selecting circuit 16 can be deactivated prior to deactivation of the word line WL.

摘要翻译： 提供了一种本发明的半导体存储器件及其控制方法，其能够防止由于地址信号的转变而导致的去活动状态和数据访问而不伴随访问时间的延迟，从而防止存储器单元的数据保持特性 恶化 基于在预充电信号PRE之前输出到毛刺消除器20的输入信号EXBn，列选择电路16被去激活，以防止同时选择列选择信号CLn和字线WL的停止。 这种方式代替了将被添加到信号CAGn的延迟时间tauD，由此消除了由于地址CAn的转换导致的毛刺噪声。 因此，地址访问时间，即从地址CAn的转换到列选择信号CLn的选择，被保持在最短访问时间tAAX0中，并且列选择电路16可以在字线WL的去激活之前去活。

公开(公告)号：US06185137B2

公开(公告)日：2001-02-06

申请号：US09457370

申请日：1999-12-09

申请人： Hajime Sato ,  Satoru Kawamoto

发明人： Hajime Sato ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/409

摘要： A memory device, such as a DRAM, includes multiple cell blocks, each having bit lines and word lines. Block control circuits are connected to respective ones of the cell blocks. The block control circuits supply a precharge signals to their associated cell blocks. A block control circuit which is connected to a defective cell block generates a precharge signal having a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block. The block control circuit sets the precharge signal to the precharge level when the defective cell block is activated and to the reset level when it is deactivated.

摘要翻译： 诸如DRAM的存储器件包括多个单元块，每个单元块具有位线和字线。 块控制电路连接到相应的单元块。 块控制电路向其相关联的单元块提供预充电信号。 连接到不良单元块的块控制电路根据缺陷单元块的访问条件生成具有位线的预充电电平和字线的复位电平的预充电信号。 当有缺陷的单元块被激活时，块控制电路将预充电信号设置为预充电电平，并且在停用时将其设置为复位电平。

公开(公告)号：US6084384A

公开(公告)日：2000-07-04

申请号：US260130

申请日：1999-03-01

申请人： Satoru Kawamoto ,  Tsukasa Kaneko ,  Yasumitsu Tanaka

发明人： Satoru Kawamoto ,  Tsukasa Kaneko ,  Yasumitsu Tanaka

IPC分类号： B60R16/033 ,  B60L1/00 ,  H02J7/00 ,  H02J7/14 ,  G05F1/56 ,  H02G3/00

CPC分类号： H02J7/0063 ,  B60L1/00 ,  H02J7/1438

摘要： A compact power supply circuit which can supply power to various apparatuses and circuits with a high degree of stability. A primary constant voltage circuit is connected to a second power supply line, which is supplied with power from a battery only when a relay is closed. The circuit supplies power to a third power supply line at a constant primary voltage. An auxiliary constant voltage circuit is connected to a first power supply line, which is always supplied with power from the battery for supplying power to the third power supply line at a constant auxiliary voltage lower than the primary voltage. A halt control circuit enables the operation of the auxiliary constant voltage circuit if power is supplied to the second power supply line and disables the operation of the auxiliary constant voltage circuit if the supply of power is interrupted for a period equal to or longer than a predetermined allowable time. The supply of power to the third power supply line is continued by the auxiliary constant voltage circuit if the temporary interruption of the supply of power to the second power supply line is within the allowable time.

摘要翻译： 能够以高稳定性向各种装置和电路供电的小型电源电路。 初级恒压电路连接到第二电源线，仅在继电器闭合时由电池从电池供电。 该电路以恒定的一次电压向第三电源线供电。 辅助恒压电路连接到第一电源线，该第一电源线总是以比初级电压低的恒定辅助电压从电池向第三电源线供电的电力供电。 如果向第二电源线提供电力，则停止控制电路能够操作辅助恒压电路，并且如果电力供应在等于或大于预定的时间段的情况下被中断，则禁止辅助恒压电路的操作 允许时间。 如果向第二电源线供电的暂时中断在允许时间内，则通过辅助恒压电路继续向第三电源线供电。

公开(公告)号：US07675801B2

公开(公告)日：2010-03-09

申请号：US12273269

申请日：2008-11-18

申请人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

发明人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4068

摘要： A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

摘要翻译： 用于半导体存储器件的刷新方法具有高抗噪性，较低的功耗和较低的成本。 在自刷新模式中未被选择的一个或多个存储单元块的所有字线被控制为具有基本上处于地平面的浮动电位。 即使当字线和位线短路时，该控制也可以防止可能由噪声引起的存储单元信息的破坏，并且还防止漏电流的产生。 不需要用于防止产生泄漏电流的保险丝等，从而实现较低的成本。