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101 条记录 (耗时 0.024 秒)

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06418072B2

    公开(公告)日：2002-07-09

    申请号：US09750352

    申请日：2000-12-29

    申请人： Yoshichika Nakaya ,  Shinichiro Ikeda ,  Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Yoshichika Nakaya ,  Shinichiro Ikeda ,  Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

    摘要翻译： 第一开关电路根据多个测试模式中的每一个从输入/输出数据中选择预定位的数据，并输出所选择的数据作为测试数据。 第二开关电路接收测试数据和输入/输出数据的每一位，并根据操作模式选择输入/输出数据和测试数据之一。 详细地说，输入/输出数据的每一位在正常操作模式下分别输出到存储单元，在测试模式期间，选择测试数据作为公共输入/输出数据输出到存储单元。 因此，可以通过使用简单的第一和第二开关电路来执行用于多种数据压缩测试的写入控制。 结果，可以减少用于数据压缩测试的控制电路的布局尺寸。

    Semiconductor memory device and method of controlling the semiconductor memory device
    3.
    发明申请
    Semiconductor memory device and method of controlling the semiconductor memory device 失效
    半导体存储器件和控制半导体存储器件的方法

    公开(公告)号：US20070237014A1

    公开(公告)日：2007-10-11

    申请号：US11806721

    申请日：2007-06-04

    申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

    摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

    摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

    Semiconductor memory device and method of controlling the semiconductor memory device
    6.
    发明申请
    Semiconductor memory device and method of controlling the semiconductor memory device 有权
    半导体存储器件和控制半导体存储器件的方法

    公开(公告)号：US20050157574A1

    公开(公告)日：2005-07-21

    申请号：US11058302

    申请日：2005-02-16

    申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4094

    CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

    摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

    摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

    Semiconductor memory device and control method thereof
    7.
    发明授权
    Semiconductor memory device and control method thereof 有权
    半导体存储器件及其控制方法

    公开(公告)号：US06847540B2

    公开(公告)日：2005-01-25

    申请号：US10404153

    申请日：2003-04-02

    申请人： Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C11/404 ,  G11C7/14 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

    CPC分类号： G11C7/227 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

    摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

    摘要翻译： 即使当器件状态从电源电容器的所有电荷存储节点中的没有存储电荷的状态改变到接通操作状态时，单元板电位也不波动的半导体存储器件包括NMOS晶体管M1 到Mk，用于将来自参考电压生成电路的参考电压VPR的线路VPR作为用于参考电压VCP的馈线（用于参考电压VCP的馈线）的每个单元块B1至Bk中的参考电压产生电路连接。 NMOS晶体管M1至Mk的栅极端子连接到公共信号phiCPR。 信号phiCPR在上电之后的预定时间输出正逻辑电平。 通过在每个单元块B1至Bk中设置用于使线VPR与线VCP短路的NMOS晶体管M1至Mk，在每个单元块B1至Bk中两条线都短路。

    Semiconductor memory device and control method thereof
    9.
    发明授权
    Semiconductor memory device and control method thereof 有权

    公开(公告)号：US06567298B2

    公开(公告)日：2003-05-20

    申请号：US09983148

    申请日：2001-10-23

    申请人： Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C1124

    CPC分类号： G11C7/227 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

    摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal &phgr;CPR. The signal &phgr;CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

    Semiconductor memory device and method for setting stress voltage
    10.
    发明授权
    Semiconductor memory device and method for setting stress voltage 失效
    半导体存储器件及设定应力电压的方法

    公开(公告)号：US06297999B2

    公开(公告)日：2001-10-02

    申请号：US09784181

    申请日：2001-02-16

    申请人： Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C2900

    CPC分类号： G11C29/50 ,  G11C11/401

    摘要： The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

    摘要翻译： 本发明提供一种执行老化测试的半导体存储器件。 该器件包括字线，位线对，存储器单元，连接到位线对的读出放大器，用于放大相关联的位线对之间的电位差，以及用于提供应力电压的老化测试控制电路 多个字线和位线对，以基于老化控制信号进行老化测试。老化测试控制电路包括：电位差设定电路，用于选择一个第一字线以产生 至少一对位线之间的电位差。 读出放大器放大电位差，以在字线和相关的位线对之间以及该对的位线之间提供应力电压。