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201 条记录 (耗时 0.072 秒)

    Power over ethernet controller integrated circuit architecture
    22.
    发明申请
    Power over ethernet controller integrated circuit architecture 有权
    通过以太网控制器集成电路架构

    公开(公告)号：US20070170909A1

    公开(公告)日：2007-07-26

    申请号：US11653875

    申请日：2007-01-17

    申请人： Pieter Vorenkamp ,  Agnes Woo ,  Anil Tammineedi ,  Ichiro Fujimori ,  David Chin ,  John Perzow

    发明人： Pieter Vorenkamp ,  Agnes Woo ,  Anil Tammineedi ,  Ichiro Fujimori ,  David Chin ,  John Perzow

    IPC分类号： G01R19/00

    CPC分类号： G06F1/26 ,  G06F1/266 ,  H04B3/44 ,  H04L12/10 ,  H04L12/40045 ,  H04L25/02 ,  Y10S370/91 ,  Y10T307/724

    摘要： Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. During detection, if the PSE finds the PD to be non-compatible, the PSE can prevent the application of power to that PD device, protecting the PD from possible damage.

    摘要翻译： 以太网供电（PoE）通信系统通过相同的通信链路提供电力和数据通信，其中电源设备（PSE）向被动设备（PD）提供DC电力（例如，48伏DC）。 DC功率通过相同的通信介质同时传输，高速数据从一个节点到另一个节点。 PSE通常包括控制器，其控制在通信链路的第二节点处提供给PD的DC电力。 PSE控制器测量输出和输入直流电源线路的电压，电流和温度，以表征PD的功率需求。 此外，PSE控制器可以检测并验证兼容的PD，确定被验证的PD的功率分类签名，PD的供电，监视功率，以及当不再请求电源时，从PD减少或去除电源 或必需。 在检测期间，如果PSE发现PD不兼容，则PSE可以阻止对该PD设备施加电力，从而保护PD免受可能的损坏。

    Integrated circuit with multiple independent power supply zones
    27.
    发明申请
    Integrated circuit with multiple independent power supply zones 有权
    具有多个独立电源区的集成电路

    公开(公告)号：US20050286192A1

    公开(公告)日：2005-12-29

    申请号：US11166954

    申请日：2005-06-24

    申请人： Sumant Ranganathan ,  Pieter Vorenkamp ,  Neil Kim ,  Chun-ying Chen

    发明人： Sumant Ranganathan ,  Pieter Vorenkamp ,  Neil Kim ,  Chun-ying Chen

    IPC分类号： H02H3/20 ,  H05K1/02 ,  H05K1/18

    CPC分类号： H05K1/0262 ,  H05K1/181 ,  Y10T307/50

    摘要： An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.

    摘要翻译： 一种集成电路，包括在基本上相同的电压电平下的多个独立电源区域以及用于利用这种电源区域的方法。 集成电路可以包括第一模块，并且可以例如包括第二模块。 第一电源总线可以将第一电力传送到第一模块，其中第一电功率由包括第一电压电平的第一组功率特性表征。 第二电源总线可以向第二模块通信第二功率，其中第二功率由包括基本上类似于第一电压电平的第二电压电平的第二组功率特性表征。 第二组功率特性可以例如与第一组功率特性基本上不同。 第二电源总线也可以例如将第二电力传送到第一模块。

    Phase locked loop
    28.
    发明授权
    Phase locked loop 有权
    锁相环

    公开(公告)号：US06963248B2

    公开(公告)日：2005-11-08

    申请号：US10783563

    申请日：2004-02-23

    申请人： Christopher M. Ward ,  Pieter Vorenkamp

    发明人： Christopher M. Ward ,  Pieter Vorenkamp

    IPC分类号： H01F17/00 ,  H01L27/08 ,  H03B5/12 ,  H03B5/36 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L7/06 ,  H03B5/32

    CPC分类号： H03J3/185 ,  H01F17/0006 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L27/08 ,  H03B5/364 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J2200/10

    摘要： A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

    摘要翻译： 周期性信号发生电路包括适于集成在半导体衬底上的差分晶体振荡器。 振荡器利用外部晶体作为谐振器。 电路被设计成使得谐振器引线上存在差分正弦信号以提供干扰信号的优异的噪声抑制。 在整个振荡器中保持差分信号传输以抑制由衬底上可能存在的其它电路产生的噪声。 由于产生了受控正弦波幅度和低谐波含量的差分信号，因此通过电源，基板，接合线和焊盘从振荡器辐射的噪声被减小。 振荡器产生低相位噪声，使振荡器可用于对失真敏感的应用中，如电视接收机。 该电路是具有低抖动的方波，从而减少数字电路产生的抖动，这将会利用该方波时钟信号。

    Reference ladder having improved feedback stability
    29.
    发明申请
    Reference ladder having improved feedback stability 有权

    公开(公告)号：US20050134363A1

    公开(公告)日：2005-06-23

    申请号：US11056198

    申请日：2005-02-14

    申请人： Pieter Vorenkamp

    发明人： Pieter Vorenkamp

    IPC分类号： H03M1/06 ,  H03M1/36

    CPC分类号： H03M1/0602 ,  H03M1/365

    摘要： A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks. An alternate embodiment includes first and second resistor ladders that are configured to generate substantially identical voltages across their respective taps. First and second feedback networks sense voltages on the first resistor ladder and control current sources that drive both the first resistor ladder and the second resistor ladder. Differential input stages that are connected to the taps of the second resistor ladder and are at least partially isolated from the feedback networks that are connected to the first resistor ladder, thereby improving stability of the feedback networks.

    Slew rate controlled output buffer
    30.
    发明授权
    Slew rate controlled output buffer 有权
    压摆率控制输出缓冲器

    公开(公告)号：US06903588B2

    公开(公告)日：2005-06-07

    申请号：US10413519

    申请日：2003-04-15

    申请人： Pieter Vorenkamp

    发明人： Pieter Vorenkamp

    IPC分类号： H03K19/003 ,  H03K5/12

    CPC分类号： H03K19/00361

    摘要： An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

    摘要翻译： 输出缓冲器包括耦合在输入和输出端子之间的第一和第二电路部分。 每个电路部分包括电容元件; 具有耦合到所述电容元件的栅极的输出晶体管和驱动所述输出端子处的电压的漏极; 以及电流发生器，其被配置为响应于所述输入端子处的逻辑转换而产生针对所述电容元件的充电电流，其中所述充电电流在所述输出晶体管的栅极处形成基本线性的斜坡电压，由此所述斜坡 电压控制输出端电压的转换速率。