公开(公告)号：US08004911B2

公开(公告)日：2011-08-23

申请号：US12662720

申请日：2010-04-29

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

摘要翻译： 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

公开(公告)号：US07362648B2

公开(公告)日：2008-04-22

申请号：US11251787

申请日：2005-10-18

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

公开(公告)号：US20060083081A1

公开(公告)日：2006-04-20

申请号：US11251787

申请日：2005-10-18

申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

摘要翻译： 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导信号。

公开(公告)号：US09786387B2

公开(公告)日：2017-10-10

申请号：US14729295

申请日：2015-06-03

申请人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Jong-Pil Son ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G11C11/15 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

公开(公告)号：US08514648B2

公开(公告)日：2013-08-20

申请号：US13051998

申请日：2011-03-18

申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

IPC分类号： G11C17/18

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

公开(公告)号：US08514610B2

公开(公告)日：2013-08-20

申请号：US13616039

申请日：2012-09-14

申请人： Sang-Woong Shin ,  Seong-Jin Jang

发明人： Sang-Woong Shin ,  Seong-Jin Jang

IPC分类号： G11C7/02

CPC分类号： G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/24

摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.

摘要翻译： 半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。 虚拟位线位于位线的外部区域。 虚拟字线在字线的外部区域。 虚拟位线保持在浮置状态。 虚拟字线保持关闭电压。

公开(公告)号：US20130135956A1

公开(公告)日：2013-05-30

申请号：US13483719

申请日：2012-05-30

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

公开(公告)号：US08295114B2

公开(公告)日：2012-10-23

申请号：US12656984

申请日：2010-02-22

申请人： Sang-Woong Shin ,  Seong-Jin Jang

发明人： Sang-Woong Shin ,  Seong-Jin Jang

IPC分类号： G11C7/02

CPC分类号： G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/24

摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.

摘要翻译： 半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。 虚拟位线位于位线的外部区域。 虚拟字线在字线的外部区域。 虚拟位线保持在浮置状态。 虚拟字线保持关闭电压。

公开(公告)号：US08184495B2

公开(公告)日：2012-05-22

申请号：US12580585

申请日：2009-10-16

申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

摘要翻译： 用于控制延迟锁定环（DLL）电路的操作的半导体存储器件包括接收外部时钟信号并对外部时钟信号和内部时钟信号执行锁定操作的DLL电路，从而获得锁定状态 。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

公开(公告)号：US20110267915A1

公开(公告)日：2011-11-03

申请号：US13051998

申请日：2011-03-18

申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。