利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.026 秒)

    Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof
    21.
    发明授权
    Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof 失效
    用于内部校正占空比的延迟锁定环路电路和占空比校正方法

    公开(公告)号：US07184509B2

    公开(公告)日：2007-02-27

    申请号：US10619821

    申请日：2003-07-14

    申请人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    发明人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    IPC分类号： H03D3/24 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K5/1565 ,  H03L7/089

    摘要： A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.

    摘要翻译： 具有占空比校正器（DCC）的占空比校正器（DCC）的延迟锁定环路（DCC）具有宽范围的占空比校正，仅消耗少量功率，对工作频率的限制较少，并且提高了存储器件的特性 描述。 延迟锁定环电路包括用于占空比校正的附加回路以及用于控制输出信号的上升沿和下降沿的回路。 因此，延迟锁定环电路可以在不使用相位搅拌器的情况下内部校正占空比。

    Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same
    24.
    发明授权
    Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same 失效
    具有占空比校正电路的集成电路装置，其通过第一和第二分离路径接收控制信号及其操作方法

    公开(公告)号：US07015739B2

    公开(公告)日：2006-03-21

    申请号：US10793001

    申请日：2004-03-04

    申请人： Woo-Jin Lee ,  Kyu-Hyoun Kim

    发明人： Woo-Jin Lee ,  Kyu-Hyoun Kim

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

    摘要翻译： 提供了数字占空比校正电路，其包括占空比检测器电路，其被配置为分别产生与第一内部时钟信号和第二内部时钟信号相关联的第一和第二控制值。 还提供比较器电路，并且被配置为将第一控制值与第二控制值进行比较并提供比较结果。 计数器电路被配置为响应于比较结果执行加法和/或减法操作以提供数字代码。 数模转换器被配置为响应于数字代码产生第三和第四控制值。 最后，占空比校正器电路被配置为接收第一和第二外部时钟信号以及第一至第四控制值，并产生具有校正占空比的第一和第二内部时钟信号。 通过第一路径接收第一和第二控制值，并且通过不同于第一路径的第二路径接收第三和第四控制值。 还提供了操作占空比校正电路的相关方法。

    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device
    25.
    发明授权
    Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device 有权
    在半导体存储器件中具有占空比校正电路和内插电路内插时钟信号的半导体存储器件

    公开(公告)号：US06934215B2

    公开(公告)日：2005-08-23

    申请号：US10656303

    申请日：2003-09-04

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/407 ,  H03K5/05 ,  H03K5/156 ,  G11C8/00

    CPC分类号： H03K5/1565 ,  G11C7/22 ,  G11C7/222

    摘要： A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

    摘要翻译： 公开了一种具有占空比校正电路和内插半导体存储器件中的时钟信号的内插电路的半导体存储器件。 半导体存储器件包括占空比校正电路，其接收外部时钟，校正外部时钟的占空比，并输出校正的占空比。 占空比校正电路包括接收外部时钟的第一延迟锁定环，反相外部时钟，使外部时钟与反相外部时钟同步，并输出同步时钟; 接收反相外部时钟的第二个延迟锁定环，将反相外部时钟与外部时钟同步并输出同步时钟; 反相电路，其使所述第一延迟锁定环路的输出信号反相; 内插电路，用第二延迟锁定环的输出信号内插反相电路的输出信号，并输出内插信号; 以及控制电路，其响应于外部时钟的时钟频率信息来控制内插电路。

    Integrated circuit die stacks having initially identical dies personalized with switches
    26.
    发明授权
    Integrated circuit die stacks having initially identical dies personalized with switches 有权
    集成电路芯片堆栈具有最初相同的裸片，具有开关个性化

    公开(公告)号：US08780578B2

    公开(公告)日：2014-07-15

    申请号：US13556976

    申请日：2012-07-24

    申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

    摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上打开开关来个性化， 将先前通过开放式开关连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过打开第二模具上的开关进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

    Memory system with delay locked loop (DLL) bypass control
    27.
    发明授权
    Memory system with delay locked loop (DLL) bypass control 有权
    具有延迟锁定环（DLL）旁路控制的内存系统

    公开(公告)号：US08379459B2

    公开(公告)日：2013-02-19

    申请号：US12840879

    申请日：2010-07-21

    申请人： Kyu-Hyoun Kim ,  Warren E. Maule ,  Lisa C. Gower

    发明人： Kevin C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2227

    摘要： A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

    摘要翻译： 具有延迟锁定环（DLL）旁路控制的存储器系统，包括用于访问存储器的方法，包括在存储器件处接收存储器读取命令。 存储器件被配置为以DLL关闭模式操作以绕过DLL时钟作为生成读取时钟的输入。 在存储器装置处接收到DLL加电命令，并且响应于接收到DLL加电命令，在存储器件执行DLL初始化处理。 存储器读取命令在以DLL关闭模式操作的存储器件处被服务，在执行DLL初始化过程时，服务与时间重叠。 存储器装置被配置为以模拟DLL操作以利用DLL时钟作为输入，以响应于经过指定的时间段来生成读取时钟。 指定的时间段相对于接收到DLL上电命令。

    IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE
    30.
    发明申请
    IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE 有权
    通过堆叠式半导体器件实现通过硅片分散多个DIES的逻辑功能实现垂直模块堆叠

    公开(公告)号：US20120124532A1

    公开(公告)日：2012-05-17

    申请号：US12944020

    申请日：2010-11-11

    申请人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

    发明人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

    IPC分类号： G06F17/50

    CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C17/143 ,  G11C17/16 ,  G11C29/12 ,  G11C29/785 ,  G11C29/802 ,  G11C2229/763 ,  G11C2229/766 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

    摘要： A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.

    摘要翻译： 一种用于实现芯片堆叠以在多个裸片上分布逻辑功能的方法和电路，以及提供了通过硅片通过堆叠的半导体器件的裸片识别和备用，以及设置有被摄体电路的设计结构。 管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。 在每个相应的管芯中执行相应的预定义功能，并且将相应的功能结果提供给管芯堆叠中的相邻管芯。 管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。 通过组合每个管芯上的多个选择的信号来形成操作管芯签名。 使用TSV互连将芯片签名耦合到下一级相邻裸片，其中它与该芯片签名组合。