公开(公告)号：US08035159B2

公开(公告)日：2011-10-11

申请号：US11796985

申请日：2007-04-30

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US20100330767A1

公开(公告)日：2010-12-30

申请号：US12806746

申请日：2010-08-21

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L21/8234

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/7803 ,  H01L29/945 ,  H01L2223/6644 ,  H03K17/165

摘要： This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

公开(公告)号：US07786531B2

公开(公告)日：2010-08-31

申请号：US11182918

申请日：2005-07-14

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/7803 ,  H01L29/945 ,  H01L2223/6644 ,  H03K17/165

摘要： This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

摘要翻译： 本发明公开了一种新的沟槽垂直半导体功率器件，其包括形成在覆盖在沟槽栅极顶部的介电层之间的导电层之间的电容器。 在具体实施例中，沟槽垂直半导体功率器件可以是沟槽金属氧化物半导体场效应晶体管（MOSFET）功率器件。 沟槽栅极是沟槽多晶硅栅极，并且导电层是覆盖设置在沟槽多晶硅栅极顶部的多晶硅介电层的第二多晶硅层。 导电层还连接到垂直功率器件的源极。

公开(公告)号：US20090219044A1

公开(公告)日：2009-09-03

申请号：US12454004

申请日：2009-05-11

申请人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

发明人： Anup Bhalla ,  Sik K. Lui ,  Daniel Ng

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： H04L63/102 ,  G01R31/2625 ,  G01R31/2884 ,  G01R35/005 ,  H01L22/14 ,  H01L2924/0002 ,  H04L63/08 ,  H01L2924/00

摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

摘要翻译： 本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。 该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。

公开(公告)号：US20090072301A1

公开(公告)日：2009-03-19

申请号：US12313305

申请日：2008-11-18

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 至少一个有源电池还包括在沟槽之间开放的沟槽的源极触点，其中沟槽的源极触点通过源极区域开放到主体区域中，用于将源区域电连接到设置在绝缘层顶部的源极金属，其中沟槽底部 沟槽源极接触表面进一步用导电材料覆盖，以用作所述活性电池中的集成肖特基势垒二极管。 屏蔽结构设置在底部并与沟槽栅绝缘，以为沟槽栅极和肖特基二极管提供屏蔽效应。

公开(公告)号：US07436022B2

公开(公告)日：2008-10-14

申请号：US11413249

申请日：2006-04-29

申请人： Anup Bhalla ,  Daniel Ng ,  Sik K Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Sik K Lui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

摘要翻译： 本发明公开了一种半导体功率器件，其包括具有多个功率晶体管单元和接合势垒肖特基（JBS）区域的有源单元区域。 半导体功率器件包括JBS区域，其还包括多个肖特基二极管，每个肖特基二极管各自具有设置在半导体衬底的顶表面附近的外延层上的PN结，其中PN结还包括设置在外延层中的反掺杂剂区域 减少PN结附近的掺杂剂分布的突然反转，以防止PN结中的早期击穿。

公开(公告)号：US20080067584A1

公开(公告)日：2008-03-20

申请号：US11522669

申请日：2006-09-17

申请人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

发明人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US07221195B2

公开(公告)日：2007-05-22

申请号：US11083470

申请日：2005-03-18

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H03B1/00

CPC分类号： H01L27/088 ,  H01L27/0629 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2223/6644 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48247 ,  H03K17/165 ,  H01L2924/00

摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

摘要翻译： 本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。 并联FET分流瞬态电流。 分流FET用于防止MOSFET器件无意中导通。 当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。 通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

公开(公告)号：US20180138906A9

公开(公告)日：2018-05-17

申请号：US14585201

申请日：2014-12-30

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H03K17/687 ,  H01H49/00

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US20170288034A1

公开(公告)日：2017-10-05

申请号：US15499487

申请日：2017-04-27

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088

CPC分类号： H01L29/42368 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/401 ,  H01L29/4236

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.