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公开(公告)号：US20130119405A1
公开(公告)日：2013-05-16
申请号：US13295178
申请日：2011-11-14
IPC分类号： H01L29/772
CPC分类号： H01L29/0847 , H01L21/76224 , H01L29/66575 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.
摘要翻译： 本发明提供一种半导体器件。 半导体器件包括半导体衬底。 半导体器件包括设置在衬底上的栅极。 基板具有凹部。 半导体器件包括沿着凹部涂覆的沟槽衬垫。 沟槽衬垫包含半导体晶体材料。 沟槽衬垫直接邻接源极/漏极应力器件。 半导体器件还包括设置在沟槽衬垫上并填充凹槽的电介质沟槽部件。 半导体器件包括设置在衬底中的源极/漏极应力器件。 源极/漏极应力器件设置在栅极和沟槽衬垫之间。
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公开(公告)号：US08375349B2
公开(公告)日：2013-02-12
申请号：US12828591
申请日：2010-07-01
CPC分类号： G06F17/5068
摘要： A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors.
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23.发明授权公开(公告)号：US08242540B2
公开(公告)日：2012-08-14
申请号：US12813822
申请日：2010-06-11
IPC分类号： H01L21/02
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02639 , H01L21/3247 , H01L21/76224 , H01L29/20 , H01L29/66522 , H01L29/78
摘要： A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.
摘要翻译： 一种器件包括硅衬底以及与硅衬底接触的III-V族化合物半导体区域。 III-V族化合物半导体区域具有与硅衬底的U形界面，U形界面的半径小于约1000nm。
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公开(公告)号：US20120009690A1
公开(公告)日：2012-01-12
申请号：US12834617
申请日：2010-07-12
CPC分类号： H01L21/67075 , H01L21/67276 , H01L22/12
摘要： The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis.
摘要翻译： 本公开提供了一种用于原位光谱法的系统。 该系统包括使用清洁溶液清洁半导体晶片的表面的晶片清洁机。 该系统还包括耦合到晶片清洁机的光谱测定机。 光谱测定机从晶片清洁机接收清洁溶液的一部分。 在清洁期间，清洁溶液的一部分从晶片收集颗粒。 光谱测定仪可操作以基于清洁溶液的一部分分析晶片的一部分的颗粒组成，同时在颗粒组成分析期间晶片保留在晶片清洁机中。
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25.发明申请公开(公告)号：US20110304021A1
公开(公告)日：2011-12-15
申请号：US12813822
申请日：2010-06-11
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02639 , H01L21/3247 , H01L21/76224 , H01L29/20 , H01L29/66522 , H01L29/78
摘要： A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.
摘要翻译： 一种器件包括硅衬底以及与硅衬底接触的III-V族化合物半导体区域。 III-V族化合物半导体区域具有与硅衬底的U形界面，U形界面的半径小于约1000nm。
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26.发明申请Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers 有权生长III-V化合物半导体从填充中间层的沟槽公开(公告)号：US20110117730A1
公开(公告)日：2011-05-19
申请号：US12842221
申请日：2010-07-23
IPC分类号： H01L21/20
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/02463 , H01L21/0254 , H01L21/02546 , H01L21/02617 , H01L21/02639
摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
摘要翻译： 形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。 多个半导体柱由绝缘层的一部分水平隔开。 以周期性图案分配多个半导体柱。 该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。
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27.发明申请公开(公告)号：US20110086491A1
公开(公告)日：2011-04-14
申请号：US12842546
申请日：2010-07-23
IPC分类号： H01L21/762
CPC分类号： H01L21/02546 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02639 , H01L21/76224 , H01L29/045 , H01L29/0665 , H01L29/66522
摘要： A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.
摘要翻译： 形成集成电路结构的方法包括提供具有硅衬底的晶片; 在硅衬底中形成多个浅沟槽隔离（STI）区域; 以及通过去除多个STI区域的相对侧壁之间的硅衬底的顶部来形成凹陷。 硅衬底中的所有凹部的基本上所有的长边在相同的方向上延伸。 然后在凹部中外延生长III-V族化合物半导体材料。
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28.发明申请High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio 有权具有改进的接通电流比的高移动性多栅极晶体管公开(公告)号：US20100252816A1
公开(公告)日：2010-10-07
申请号：US12639653
申请日：2009-12-16
CPC分类号： H01L29/8124 , H01L29/1054 , H01L29/122 , H01L29/66431 , H01L29/66484 , H01L29/66795 , H01L29/66818 , H01L29/7831 , H01L29/785 , H01L29/812
摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.
摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。
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29.发明授权Method of forming fin field-effect transistors having controlled fin height 有权形成具有受控翅片高度的鳍状场效应晶体管的方法公开(公告)号：US09041158B2
公开(公告)日：2015-05-26
申请号：US13403630
申请日：2012-02-23
申请人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yuan-Fu Shao , Wen-Huei Guo , Tung Ying Lee
CPC分类号： H01L29/42368 , H01L21/823431 , H01L21/845 , H01L29/02 , H01L29/06 , H01L29/0653 , H01L29/7856
摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.
摘要翻译： 半导体装置包括具有受控制的翅片高度的鳍状场效应晶体管（FinFET）。 该装置包括高翅片密度区域和低翅片密度区域。 每个翅片密度区域包括翅片和翅片之间的电介质材料。 电介质材料包括用于不同翅片密度区域的不同掺杂剂浓度，并且是与沉积物相同的材料。
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公开(公告)号：US08963257B2
公开(公告)日：2015-02-24
申请号：US13293732
申请日：2011-11-10
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/66
CPC分类号： H01L29/66818 , H01L21/2236 , H01L21/823431 , H01L21/823462 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823857 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
摘要翻译： 本发明涉及Fin场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 在所述基板顶表面上方延伸的第一翅片和第二翅片，其中每个翼片具有顶表面和侧壁; 所述第一和第二翅片之间的绝缘层从所述基板顶表面向上延伸所述翅片; 覆盖第一鳍片的顶表面和第一鳍片的侧壁的第一栅极电介质和覆盖第二鳍片的顶表面和第二鳍片的侧壁的第二栅极电介质具有小于第一厚度的第二厚度; 以及穿过第一栅极电介质和第二栅极电介质两端的导电栅极条。
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