公开(公告)号：US09589982B1

公开(公告)日：2017-03-07

申请号：US14854383

申请日：2015-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

Abstract translation: 本发明的实施例提供改进的三维存储器单元，阵列，器件和/或类似物以及相关联的方法。 在一个实施例中，提供三维存储单元。 三维存储单元包括第一导电层; 与所述第一导电层间隔开的第三导电层; 连接第一导电层和第三导电层以形成具有内表面的开口的沟道导电层; 沿着由所述第一导电层，所述沟道导电层和所述第三导电层包围的所述开口的内表面设置的电介质层; 以及插入并基本上填充由电介质层形成的剩余开口部分的第二导电层。 第一导电层，电介质层和第二导电层被配置成形成阶梯结构。

公开(公告)号：US20160336339A1

公开(公告)日：2016-11-17

申请号：US14881350

申请日：2015-10-13

Applicant: Macronix International Co., Ltd.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L27/115 ,  G11C16/14 ,  H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C2216/02 ,  H01L27/11565 ,  H01L29/7926

Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.

Abstract translation: 本发明的实施例提供改进的3D非易失性存储器件和相关联的方法。 在一个实施例中，提供一串3D非易失性存储单元。 弦线包括沿着弦的轴线延伸的芯，芯在垂直于轴线的平面中具有椭圆形横截面; 以及多个字线，每个字线围绕所述芯的一部分设置，所述多个字线沿着所述轴间隔开，并且每个字线对应于所述存储器单元之一。 在各种实施例中，为了改善3D非易失性存储器件的操作，定义了至少一个操作参数。

公开(公告)号：US09048263B2

公开(公告)日：2015-06-02

申请号：US14314830

申请日：2014-06-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: H01L21/8247 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 在该方法中，在基板上形成具有突出部的第一氧化物层。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和一对电荷存储间隔物上形成第二氧化物层。 导电层形成在第二氧化物层上，其中导电层完全位于一对电荷存储间隔物的顶部上。

公开(公告)号：US20140187032A1

公开(公告)日：2014-07-03

申请号：US14198320

申请日：2014-03-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.

Abstract translation: 本发明的存储器件的制造方法至少包括以下步骤。 在衬底上形成隧道介电层。 在隧道电介质层上徘徊一扇门。 在栅极和隧道介电层之间形成至少一个电荷存储层。 在栅极旁边的衬底中形成两个掺杂区域。 字线形成在栅极上并电连接到栅极，其中字线的厚度大于栅极的厚度。