公开(公告)号：US20160118405A1

公开(公告)日：2016-04-28

申请号：US14981221

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: H01L27/115

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻栅极共享以形成多个FeFET。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

公开(公告)号：US20140169066A1

公开(公告)日：2014-06-19

申请号：US13921951

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

公开(公告)号：US20130229878A1

公开(公告)日：2013-09-05

申请号：US13847189

申请日：2013-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott N. Gatzemeier ,  Wallace E. Fister ,  Adam D. Johnson ,  Benjamin S. Louie

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/066 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

公开(公告)号：US10699784B2

公开(公告)日：2020-06-30

申请号：US16057170

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US10510423B2

公开(公告)日：2019-12-17

申请号：US15669785

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

公开(公告)号：US09779806B2

公开(公告)日：2017-10-03

申请号：US13938052

申请日：2013-07-09

Applicant: Micron Technology, Inc.

Inventor： Adam D. Johnson

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2211/5631 ,  G11C2211/5642

Abstract: Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.

公开(公告)号：US09281044B2

公开(公告)日：2016-03-08

申请号：US13897037

申请日：2013-05-17

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻的栅极共享以使多个FeFET发生。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

公开(公告)号：US09230645B2

公开(公告)日：2016-01-05

申请号：US14588593

申请日：2015-01-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

IPC: G11C11/00 ,  G11C13/00 ,  H01L21/66

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

Abstract: Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

公开(公告)号：US20140340952A1

公开(公告)日：2014-11-20

申请号：US13897037

申请日：2013-05-17

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

IPC: H01L43/02 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻的栅极共享以使多个FeFET起作用。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

公开(公告)号：US08687435B2

公开(公告)日：2014-04-01

申请号：US13847189

申请日：2013-03-19

Applicant: Micron Technology, Inc.

Inventor： Scott N. Gatzemeier ,  Wallace E. Fister ,  Adam D. Johnson ,  Benjamin S. Louie

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/066 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

Abstract translation: 公开了方法，存储器件和系统。 在一个实施例中，非易失性存储器件通过接收地址信号和写数据信号并发送读数据信号的相同输入/输出端接收命令信号。 输入/输出端连接到多路复用器，其响应于接收模式控制信号将输入/输出端子耦合到命令总线或输入/输出总线。 当模式控制信号使输入/输出端子耦合到输入/输出总线时，存储器件中的锁存器锁存命令信号。 结果，命令信号继续应用于命令总线。 当模式控制信号使得输入/输出端子耦合到输入/输出总线时，写数据信号被计时到存储器件中，并且响应于所接收的时钟信号将读出的数据信号从存储器件中输出。