公开(公告)号：US20190279704A1

公开(公告)日：2019-09-12

申请号：US16235163

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/4074 ,  G06F3/06

Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.

公开(公告)号：US10354712B2

公开(公告)日：2019-07-16

申请号：US16104709

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11502 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US20190013057A1

公开(公告)日：2019-01-10

申请号：US16131969

申请日：2018-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  H01L27/11509 ,  H01L27/11507 ,  H01L27/11504 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C11/2275 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/4091 ,  G11C11/5657 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and, for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US20180374528A1

公开(公告)日：2018-12-27

申请号：US16058202

申请日：2018-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11509 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US10127965B2

公开(公告)日：2018-11-13

申请号：US15679032

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11507 ,  G11C11/56

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US20180061469A1

公开(公告)日：2018-03-01

申请号：US15679016

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11509 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US12080336B2

公开(公告)日：2024-09-03

申请号：US17662198

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiyun Li ,  Christopher J. Kawamura ,  Tae H. Kim

IPC: G11C11/4091 ,  H03F3/45

CPC classification number: G11C11/4091 ,  H03F3/45264

Abstract: Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

公开(公告)号：US20220254388A1

公开(公告)日：2022-08-11

申请号：US17172257

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Beau D. Barry ,  Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/30 ,  G11C16/32

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

公开(公告)号：US11176987B2

公开(公告)日：2021-11-16

申请号：US17114404

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US10910379B2

公开(公告)日：2021-02-02

申请号：US16354450

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mitsunari Sukekawa ,  Yusuke Yamamoto ,  Christopher J. Kawamura ,  Hiroaki Taketani

IPC: H01L27/108 ,  H01L23/528

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.