公开(公告)号：US20190392887A1

公开(公告)日：2019-12-26

申请号：US16556763

申请日：2019-08-30

Applicant: Micron Technology, Inc.

Inventor： Yu-Feng Chen ,  Byung S. Moon ,  Myung Ho Bae ,  Harish N. Venkata

IPC: G11C11/4074 ,  G11C11/408 ,  G06F13/42

Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.

公开(公告)号：US10388333B2

公开(公告)日：2019-08-20

申请号：US15797759

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20 ,  G11C7/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US10360949B2

公开(公告)日：2019-07-23

申请号：US15972783

申请日：2018-05-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US20190198088A1

公开(公告)日：2019-06-27

申请号：US16049576

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G11C11/4091 ,  G11C11/408

Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.

公开(公告)号：US20190179560A1

公开(公告)日：2019-06-13

申请号：US15837685

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0685 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1018 ,  G11C7/20 ,  G11C8/04 ,  G11C11/4072 ,  G11C29/022 ,  G11C29/028 ,  G11C29/46 ,  G11C29/52

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US10242722B2

公开(公告)日：2019-03-26

申请号：US15978578

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US10068664B1

公开(公告)日：2018-09-04

申请号：US15600409

申请日：2017-05-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Guy S. Perry ,  Harish N. Venkata ,  Glen E. Hush

IPC: G11C29/00

CPC classification number: G11C29/702 ,  G11C29/785 ,  G11C29/81 ,  G11C29/848

Abstract: Apparatuses and methods related to column repair in memory are described. An apparatus can include sensing circuitry. The sensing circuitry can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

公开(公告)号：US09966116B2

公开(公告)日：2018-05-08

申请号：US15693064

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/222 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US09224436B2

公开(公告)日：2015-12-29

申请号：US13902591

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/18 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods for memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了具有单独的全局读写线和/或读出放大器区列选择线的存储器阵列的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。

公开(公告)号：US20140347945A1

公开(公告)日：2014-11-27

申请号：US13902591

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了与具有单独的全局读写线和/或读出放大器区域列选择线的存储器阵列相关的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。