公开(公告)号：US20190288691A1

公开(公告)日：2019-09-19

申请号：US16430258

申请日：2019-06-03

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: H03K21/40 ,  G11C8/06 ,  G11C7/10 ,  H03K19/21 ,  H03K21/10 ,  G06F5/06

Abstract: Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

公开(公告)号：US10354701B2

公开(公告)日：2019-07-16

申请号：US16200443

申请日：2018-11-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4063 ,  H03K19/003 ,  H03K19/0175 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/4093

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

公开(公告)号：US20190101975A1

公开(公告)日：2019-04-04

申请号：US16205356

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G06F3/00 ,  G11C7/10 ,  G11C11/4063 ,  G06F13/16

CPC classification number: G06F3/002 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  G11C2207/2272

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

公开(公告)号：US10063240B2

公开(公告)日：2018-08-28

申请号：US15684734

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: H03K19/21 ,  H03K21/40 ,  G11C7/10 ,  H03K21/10

CPC classification number: H03K21/40 ,  G06F5/06 ,  G11C7/1087 ,  G11C7/109 ,  G11C8/06 ,  H03K19/21 ,  H03K21/10

Abstract: Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

公开(公告)号：US20160314823A1

公开(公告)日：2016-10-27

申请号：US14693769

申请日：2015-04-22

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

Abstract translation: 公开了用于减少多个命令移位器的装置和方法。 示例性设备包括编码器电路，等待时间移位器电路和解码器电路。 编码器电路可以被配置为对命令进行编码，其中根据命令类型对命令进行编码，并且耦合到编码器电路的等待时间移位器电路可被配置为为已编码的命令提供等待时间。 耦合到等待时间移位器电路的解码器电路可以被配置为对编码的命令进行解码，并提供解码的命令以执行与解码的命令的命令类型相关联的存储器操作。

公开(公告)号：US20150071022A1

公开(公告)日：2015-03-12

申请号：US14022102

申请日：2013-09-09

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C8/10 ,  G11C2207/2272

Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

Abstract translation: 描述了用于向命令路径电路提供有源和非活动时钟信号的装置和方法。 一个示例性方法包括向命令路径提供活动时钟信号用于命令循环的第一部分用于背靠背命令的命令。 命令路径对命令进行解码，并响应于时钟信号提供输出命令信号。 该方法还包括向命令路径提供用于命令循环命令的命令循环的第二部分的非活动时钟信号。

公开(公告)号：US12073913B2

公开(公告)日：2024-08-27

申请号：US17821740

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.

公开(公告)号：US20240071436A1

公开(公告)日：2024-02-29

申请号：US17821740

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.

公开(公告)号：US11727979B2

公开(公告)日：2023-08-15

申请号：US17369055

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  William C. Waldrop ,  Vijayakrishna J. Vankayala

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/2254

Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

公开(公告)号：US11615821B1

公开(公告)日：2023-03-28

申请号：US17513830

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Navya Sri Sreeram ,  Kallol Mazumder

IPC: G11C7/10

Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.