公开(公告)号：US20240274184A1

公开(公告)日：2024-08-15

申请号：US18632024

申请日：2024-04-10

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/22 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US11984150B2

公开(公告)日：2024-05-14

申请号：US17821646

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/40 ,  G11C11/22 ,  G11C11/408 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20240071466A1

公开(公告)日：2024-02-29

申请号：US17821646

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/22 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20230395164A1

公开(公告)日：2023-12-07

申请号：US17831266

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Kijun Nam ,  Mingdong Cui

IPC: G11C16/30 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/30 ,  G11C16/12 ,  G11C16/3418

Abstract: In some aspects, the techniques described herein relate to a circuit including: a memory cell; a source follower, a source terminal of the source follower communicatively coupled to the memory cell; a voltage source; an operational amplifier, a non-inverting input of the operational amplifier communicatively coupled to the voltage source; and a replica source follower, a gate of the replica source follower communicatively coupled to an output of the operational amplifier and a source terminal of the replica source follower communicatively coupled to an inverting input of the operational amplifier via a feedback loop.

公开(公告)号：US20230395129A1

公开(公告)日：2023-12-07

申请号：US17831332

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Jin Seung Son ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4096

Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.

公开(公告)号：US11367483B2

公开(公告)日：2022-06-21

申请号：US17089146

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： Josephine T. Hamada ,  Mingdong Cui ,  Joseph M. McCrate ,  Karthik Sarpatwari ,  Jessica Chen

IPC: G11C7/22 ,  G11C13/00 ,  H01L45/00 ,  G11C5/14

Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

公开(公告)号：US20220076770A1

公开(公告)日：2022-03-10

申请号：US17013089

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Nevil N. Gajera ,  Mingdong Cui ,  Fabio Pellizzer

IPC: G11C29/38

Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

公开(公告)号：US20210366540A1

公开(公告)日：2021-11-25

申请号：US17394778

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

公开(公告)号：US11139034B1

公开(公告)日：2021-10-05

申请号：US16929884

申请日：2020-07-15

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US20210151107A1

公开(公告)日：2021-05-20

申请号：US17089146

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： Josephine T. Hamada ,  Mingdong Cui ,  Joseph M. McCrate ,  Karthik Sarpatwari ,  Jessica Chen

IPC: G11C13/00 ,  H01L45/00 ,  G11C5/14

Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.