公开(公告)号：US20230215489A1

公开(公告)日：2023-07-06

申请号：US18182305

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/003 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2211/4013

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US11568940B2

公开(公告)日：2023-01-31

申请号：US17408774

申请日：2021-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.

公开(公告)号：US20220130447A1

公开(公告)日：2022-04-28

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Embodiments relate to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. Embodiments are directed to writing and reading memory cell pairs.

公开(公告)号：US10714191B2

公开(公告)日：2020-07-14

申请号：US16410406

申请日：2019-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US10388384B2

公开(公告)日：2019-08-20

申请号：US16043259

申请日：2018-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C11/56 ,  G11C16/26 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US20190066804A1

公开(公告)日：2019-02-28

申请号：US16043259

申请日：2018-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C29/02 ,  G06F11/07 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/073 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US10121544B2

公开(公告)日：2018-11-06

申请号：US15692565

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C11/56 ,  G11C16/32

Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.

公开(公告)号：US10096365B2

公开(公告)日：2018-10-09

申请号：US15489276

申请日：2017-04-17

Applicant: Micron Technology, Inc.

Inventor： Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G06F3/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

公开(公告)号：US10062441B1

公开(公告)日：2018-08-28

申请号：US15692154

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/073 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

Abstract: Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw data value as their respective raw data value; determining a respective raw data values representative of transition between each pair of adjacent data states responsive to the determined numbers of memory cells of the first subset of the plurality of memory cells for each raw data value; and determining a respective data state of the plurality of data states for each memory cell of a second subset of the plurality of memory cells responsive to its respective raw data value and to the determined raw data values representative of the transitions between adjacent data states.

公开(公告)号：US10037797B2

公开(公告)日：2018-07-31

申请号：US15687710

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Ramin Ghodsi

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/12 ,  G11C16/04 ,  G11C16/34 ,  G06F3/06 ,  G06F12/02 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.