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公开(公告)号：US20240143501A1
公开(公告)日：2024-05-02
申请号：US18494841
申请日：2023-10-26
Applicant: Micron Technology, Inc.
Inventor： Luca Nubile , Luigi Pilolli , Liang Yu , Ali Mohammadzadeh , Walter Di Francesco , Biagio Iorio
CPC classification number: G06F12/0246 , G06F1/28
Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.
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22.发明公开公开(公告)号：US20240071510A1
公开(公告)日：2024-02-29
申请号：US17899409
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Giovanni Maria Paolucci , Dave Scott Ebsen , James Fitzpatrick , Akira Goda , Jeffrey S. McNeil , Umberto Siciliani , Daniel J. Hubbard , Walter Di Francesco , Michele Incarnati
CPC classification number: G11C16/102 , G11C16/08 , G11C16/3404
Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
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公开(公告)号：US20230298680A1
公开(公告)日：2023-09-21
申请号：US18110489
申请日：2023-02-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Umberto Siciliani , Violante Moschiano , Walter Di Francesco , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/20
Abstract: Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.
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公开(公告)号：US20230065421A1
公开(公告)日：2023-03-02
申请号：US17675526
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Walter Di Francesco , Violante Moschiano , Umberto Siciliani
IPC: G11C16/10 , G11C16/04 , G06F12/0802
Abstract: Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.
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公开(公告)号：US20220083241A1
公开(公告)日：2022-03-17
申请号：US16948426
申请日：2020-09-17
Applicant: Micron Technology, Inc.
Inventor： Luca Nubile , Ali Mohammadzadeh , Biagio Iorio , Walter Di Francesco , Yuanhang Cao , Luca De Santis , Fumin Gu
IPC: G06F3/06
Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.
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Patent Agency Ranking
公开(公告)号：US20200027514A1
公开(公告)日：2020-01-23
申请号：US16040382
申请日：2018-07-19
Applicant: Micron Technology, Inc.
Inventor： Michael G. Miller , Kishore Kumar Muchherla , Harish R. Singidi , Walter Di Francesco , Renato C. Padilla , Gary F. Besinga , Violante Moschiano
Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.
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公开(公告)号：US10423350B2
公开(公告)日：2019-09-24
申请号：US15532886
申请日：2017-01-23
Applicant: Micron Technology, Inc.
Inventor： Sivagnanam Parthasarathy , Terry M. Grunzke , Lucia Botticchio , Walter Di Francesco , Vamshi K. Indavarapu , Gianfranco Valeri , Renato C. Padilla , Ali Mohammadzadeh , Jung Sheng Hoei , Luca De Santis
IPC: G06F3/06 , G06F12/02 , G06F12/1009
Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
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公开(公告)号：US20170235637A1
公开(公告)日：2017-08-17
申请号：US15583678
申请日：2017-05-01
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
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公开(公告)号：US09639420B2
公开(公告)日：2017-05-02
申请号：US14657878
申请日：2015-03-13
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
CPC classification number: G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
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公开(公告)号：US20160266966A1
公开(公告)日：2016-09-15
申请号：US14657878
申请日：2015-03-13
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
CPC classification number: G06F11/1076 , G06F11/1048 , G06F11/1068 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
Abstract translation: 存储器件包括包括缓冲器数据的存储器阵列。 存储器装置还包括存储器控制器。 存储器控制器包括纠错码（ECC）组件。 存储器控制器还接收与ECC组件分析的状态命令和与数据质量有关的指示。 基于状态值，存储器控制器经由ECC组件利用多个纠错技术之一来校正错误（例如，软状态，校准等）。
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