公开(公告)号：US12052869B2

公开(公告)日：2024-07-30

申请号：US17475932

申请日：2021-09-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

公开(公告)号：US11985822B2

公开(公告)日：2024-05-14

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11582 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20240136305A1

公开(公告)日：2024-04-25

申请号：US17972953

申请日：2022-10-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

公开(公告)号：US20230377633A1

公开(公告)日：2023-11-23

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/063

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US20230371252A1

公开(公告)日：2023-11-16

申请号：US17742159

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Teng-Hao Yeh ,  Chia-Jung Chiu

IPC: H01L27/11526 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

CPC classification number: H01L27/11526 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.

公开(公告)号：US20230269944A1

公开(公告)日：2023-08-24

申请号：US18308594

申请日：2023-04-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L21/0217

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

公开(公告)号：US20230134957A1

公开(公告)日：2023-05-04

申请号：US17569419

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/10 ,  G11C16/04 ,  G11C5/02 ,  H01L23/34

Abstract: A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.

公开(公告)号：US20230070119A1

公开(公告)日：2023-03-09

申请号：US17695943

申请日：2022-03-16

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh

IPC: H01L27/11

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

公开(公告)号：US11257547B2

公开(公告)日：2022-02-22

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan Hsu ,  Po-Kai Hsu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/14 ,  G06N3/04 ,  G11C11/56

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

公开(公告)号：US11011234B1

公开(公告)日：2021-05-18

申请号：US16736029

申请日：2020-01-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yi-Ching Liu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.