公开(公告)号：US07511582B2

公开(公告)日：2009-03-31

申请号：US10623992

申请日：2003-07-21

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H04J3/0688

Abstract: The present invention provides a clock circuit to produce a Reference Clock Signal used to latch data between first bit stream(s) and second bit stream(s), wherein the number and bit rate of the first bit stream(s) and the second bit stream(s) differ. The VCO generates one of a number of inputs to a PLL within the clock circuit. At a minimum, these inputs include a first bit stream data clock. Additionally, these inputs may further include a Loop Timing Clock Signal, an External Reference Clock Signal, and/or a Reverse Clock Signal for the PLL. The input provided by the VCO make up a VCO Output Signal wherein a filtering circuit that circuit includes a capacitor and a resistor reduces noise contained within the VCO Output Signal.

Abstract translation: 本发明提供了一种时钟电路，用于产生用于在第一比特流和第二比特流之间锁存数据的参考时钟信号，其中第一比特流和第二比特流的数量和比特率 流不同。 VCO产生时钟电路内的PLL的多个输入之一。 至少这些输入包括第一位流数据时钟。 此外，这些输入还可以包括用于PLL的环路定时时钟信号，外部参考时钟信号和/或反向时钟信号。 由VCO提供的输入构成VCO输出信号，其中包括电容器和电阻的电路的滤波电路减少了VCO输出信号中包含的噪声。

公开(公告)号：US20050156653A1

公开(公告)日：2005-07-21

申请号：US11078151

申请日：2005-03-11

Applicant: Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

Inventor： Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC: H03K19/0185 ,  H04L7/00 ,  H03L5/00

CPC classification number: H03K19/018585 ,  H04L7/0008

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract translation: 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US06690949B1

公开(公告)日：2004-02-10

申请号：US09410136

申请日：1999-09-30

Applicant: Danny Shamlou ,  Guangming Yin ,  Ricke Waylan Clark ,  Paul A. Underbrink

Inventor： Danny Shamlou ,  Guangming Yin ,  Ricke Waylan Clark ,  Paul A. Underbrink

IPC: H04B138

CPC classification number: H04B1/406

Abstract: A communication system for the wireless transmission of information through a single antenna is disclosed. The communication system comprises a handset and one or more modules capable of being coupled to the handset. The handset processes baseband information signals being received and transmitted, and transmits and receives radio frequency (RF) information signals through its antenna. Each module is removably couplable to the handset for converting baseband information signals into RF information signals for transmission, and for converting received RF information signals into baseband information signals. Each removably couplable module is optimized to enable wireless communication in accordance with at least one communication standard when coupled to the handset. By coupling the appropriate module with the handset, wireless communication in a number of geographic locations may be achieved.

Abstract translation: 公开了一种用于通过单个天线无线传输信息的通信系统。 通信系统包括手机和能够耦合到手机的一个或多个模块。 手机处理接收和发送的基带信息信号，并通过其天线发送和接收射频（RF）信息信号。 每个模块可拆卸地耦合到手机，用于将基带信息信号转换成用于传输的RF信息信号，并将接收的RF信息信号转换为基带信息信号。 每个可移除耦合的模块被优化以在耦合到手机时根据至少一个通信标准实现无线通信。 通过将适当的模块与手机耦合，可以实现多个地理位置的无线通信。

公开(公告)号：US09401594B2

公开(公告)日：2016-07-26

申请号：US14374498

申请日：2012-02-15

Applicant: Quanqing Zhu ,  Guangming Yin

Inventor： Quanqing Zhu ,  Guangming Yin

IPC: H02H9/00 ,  H02H3/22 ,  H04L25/02

CPC classification number: H02H3/22 ,  H04L25/0272 ,  H04L25/028

Abstract: An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.

Abstract translation: 集成电路装置（200）包括第一和第二差分I / O引脚（TRXP / TRXN）和浪涌保护电路。 浪涌保护电路包括保护晶体管，正浪涌检测电路和负浪涌检测电路。 保护晶体管连接在第一和第二I / O引脚之间，并具有接收控制信号（CTRL）的门。 如果正浪涌检测电路检测到任一个I / O引脚上的正浪涌能量和/或如果负浪涌检测电路检测到任何一个的负浪涌能量，则保护晶体管导通以将I / O引脚连接在一起 I / O引脚。 浪涌保护电路以不会对设备性能产生不利影响的方式为以太网设备提供更高的防护性能，防止不需要的能量。

公开(公告)号：US08779859B2

公开(公告)日：2014-07-15

申请号：US13570062

申请日：2012-08-08

Applicant: Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

Inventor： Wenjun Su ,  Chiewcharn Narathong ,  Guangming Yin ,  Aristotele Hadjichristos

IPC: H03F1/22

CPC classification number: H03F1/223 ,  H03F3/193

Abstract: Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

Abstract translation: 用于产生多共源共栅放大器偏置电压的技术。 在一方面，提供了一种多共源共栅偏压网络，偏置网络中的每个晶体管是多共源共栅放大器中对应的晶体管的复制品，使多级共源共栅放大器中的晶体管能够精确偏置。 在另一方面，用于多重共源共栅放大器的电压源与用于复制偏压网络的电压源分开提供，以有利地将放大器电压源与偏置网络电压源的变化分离。 在另一方面，多并联放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压，所以可以以这种方式调节放大器的增益，而不将可变增益元件直接引入放大器信号路径。

公开(公告)号：US07142013B2

公开(公告)日：2006-11-28

申请号：US11133723

申请日：2005-05-20

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03K19/21

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

公开(公告)号：US06982583B2

公开(公告)日：2006-01-03

申请号：US10876790

申请日：2004-06-25

Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

IPC: H03K3/356

CPC classification number: H03K3/3562 ,  H03K3/356043 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract translation: 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C 3/4 MOS）逻辑。 包括逆变器/缓冲器，电平移位器，NAND，NOR，异或门，锁存器，触发器等的整个逻辑元件族都使用C 3 MOS技术实现。 通过将高速C“3”MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的三极管/ CMOS逻辑允许诸如光纤通信系统中使用的高速收发器之类的电路的更大集成。 C 3 O 3 MOS结构能够使用可能大于CMOS制造工艺所需的电压的电源电压，进一步提高电路的性能。

公开(公告)号：US20050190004A1

公开(公告)日：2005-09-01

申请号：US11120738

申请日：2005-05-03

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03B1/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract translation: 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20050134310A1

公开(公告)日：2005-06-23

申请号：US11057968

申请日：2005-02-15

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

公开(公告)号：US06624699B2

公开(公告)日：2003-09-23

申请号：US10028806

申请日：2001-10-25

Applicant: Guangming Yin ,  Jun Cao

Inventor： Guangming Yin ,  Jun Cao

IPC: H03F345

CPC classification number: H03F1/14 ,  H03F1/483 ,  H03F2203/45018 ,  H03F2203/45512 ,  H03F2203/45554 ,  H03F2203/45714

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.