公开(公告)号：US08153502B2

公开(公告)日：2012-04-10

申请号：US11434982

申请日：2006-05-16

Applicant: Li Li ,  Ronald Weimer ,  Richard Stocks ,  Chris Hill

Inventor： Li Li ,  Ronald Weimer ,  Richard Stocks ,  Chris Hill

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/31

CPC classification number: H01L21/76224

Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.

Abstract translation: 填充空腔或沟槽的方法。 更具体地，提供了填充半导体层中的空腔或沟槽的方法。 所述方法包括通过采用保形沉积工艺将第一介电层沉积到沟槽中。 接下来，蚀刻第一介电层以在第一介电层内的沟槽中产生凹陷。 然后通过采用高密度等离子体沉积工艺，用第二介电层填充凹陷。 该技术在填充具有窄宽度和/或高纵横比的空腔和沟槽中可能特别有用。

公开(公告)号：US20070269958A1

公开(公告)日：2007-11-22

申请号：US11434982

申请日：2006-05-16

Applicant: Li Li ,  Ronald Weimer ,  Richard Stocks ,  Chris Hill

Inventor： Li Li ,  Ronald Weimer ,  Richard Stocks ,  Chris Hill

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.

Abstract translation: 填充空腔或沟槽的方法。 更具体地，提供了填充半导体层中的空腔或沟槽的方法。 所述方法包括通过采用保形沉积工艺将第一介电层沉积到沟槽中。 接下来，蚀刻第一介电层以在第一介电层内的沟槽中产生凹陷。 然后通过采用高密度等离子体沉积工艺，用第二介电层填充凹陷。 该技术在填充具有窄宽度和/或高纵横比的空腔和沟槽中可能特别有用。

公开(公告)号：US20060289951A1

公开(公告)日：2006-12-28

申请号：US11513663

申请日：2006-08-31

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L21/28185 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

公开(公告)号：US20060267062A1

公开(公告)日：2006-11-30

申请号：US11496605

申请日：2006-07-31

Applicant: Scott DeBoer ,  Ronald Weimer ,  John Moore

Inventor： Scott DeBoer ,  Ronald Weimer ,  John Moore

IPC: H01L29/94

CPC classification number: H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

公开(公告)号：US20060198955A1

公开(公告)日：2006-09-07

申请号：US11416866

申请日：2006-05-03

Applicant: Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Ronald Weimer ,  David Kubista ,  Kevin Beaman ,  Cem Basceri

Inventor： Lingyi Zheng ,  Trung Doan ,  Lyle Breiner ,  Er-Xuan Ping ,  Ronald Weimer ,  David Kubista ,  Kevin Beaman ,  Cem Basceri

IPC: C23C16/00

CPC classification number: C23C16/4583 ,  C23C16/45546 ,  C23C16/45578 ,  Y10S206/832

Abstract: The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

Abstract translation: 本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。 这些设备中的一些包括微型工件保持器，其包括气体分配器。 一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。 该工件保持器包括多个工件支撑件和气体分配器。 工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。 气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

公开(公告)号：US20060138594A1

公开(公告)日：2006-06-29

申请号：US11358647

申请日：2006-02-21

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L29/00

CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

公开(公告)号：US20050101078A1

公开(公告)日：2005-05-12

申请号：US11003642

申请日：2004-12-03

Applicant: Denise Eppich ,  Ronald Weimer

Inventor： Denise Eppich ,  Ronald Weimer

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L21/00 ,  H01L21/8238

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28167 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract translation: 本发明包括形成电路装置的方法。 在导电掺杂的硅和电介质层之间形成包含不大于（或者包括不超过70个ALD循环的厚度）的厚度的含金属材料。 导电掺杂的硅可以是n型硅，并且介电层可以是高k电介质材料。 含金属材料可以直接形成在电介质层上，并且导电掺杂的硅可以直接形成在含金属的材料上。 电路器件可以是电容器结构或晶体管结构。 如果电路器件是晶体管结构，则可以将其并入CMOS组件中。 本发明的各种装置可以结合到存储器结构中，并且可以并入到电子系统中。

公开(公告)号：US20050081786A1

公开(公告)日：2005-04-21

申请号：US10687458

申请日：2003-10-15

Applicant: David Kubista ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Kevin Beaman ,  Er-Xuan Ping ,  Lingyi Zheng ,  Cem Basceri

Inventor： David Kubista ,  Trung Doan ,  Lyle Breiner ,  Ronald Weimer ,  Kevin Beaman ,  Er-Xuan Ping ,  Lingyi Zheng ,  Cem Basceri

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/00

CPC classification number: C23C16/45544 ,  C23C16/4412 ,  Y10T137/0396

Abstract: Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法在此公开。 在一个实施例中，系统包括气相反应室，连接到反应室的第一排气管线，与第一排气管线流体连通的第一和第二阱，以及耦合到第一排气管线以除去气体的真空泵 从反应室。 第一和第二捕集器独立地可操作地单独地和/或共同地从反应室收集副产物。 要强调的是提供本摘要以符合要求摘要的规则。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20050003680A1

公开(公告)日：2005-01-06

申请号：US10612836

申请日：2003-07-03

Applicant: Ronald Weimer ,  Lyle Breiner

Inventor： Ronald Weimer ,  Lyle Breiner

IPC: C23C16/30 ,  C23C16/34 ,  H01L21/28 ,  H01L21/30 ,  H01L21/314 ,  H01L21/318 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8244 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0214 ,  C23C16/308 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/10873 ,  H01L27/11 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/66825

Abstract: The invention includes methods of forming deuterated silicon nitride-containing materials from at least one deuterated nitrogen compound in combination with one or more silicon-containing compounds that do not contain hydrogen isotopes. Suitable deuterated nitrogen compounds can comprise, for example, NH2D, NHD2 and ND3. Suitable silicon-containing compounds include, for example, SiCl4 and Si2Cl6. Deuterated silicon nitride-containing materials of the present invention can be incorporated into, for example, transistor devices. The transistor devices can be utilized in DRAM cells, which in turn can be utilized in electronic systems.

Abstract translation: 本发明包括从至少一种氘代氮化合物与一种或多种不含氢同位素的含硅化合物组合形成氘代含氮化硅材料的方法。 合适的氘化氮化合物可以包括例如NH 2 D，NHD 2和ND 3。 合适的含硅化合物包括例如SiCl 4和Si 2 Cl 6。 本发明的含氘代的含氮化硅的材料可以结合到例如晶体管器件中。 晶体管器件可以用在DRAM单元中，这又可以用于电子系统中。

公开(公告)号：US20060289952A1

公开(公告)日：2006-12-28

申请号：US11513880

申请日：2006-08-31

Applicant: Ronald Weimer

Inventor： Ronald Weimer

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L21/28185 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.