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公开(公告)号：US20140286075A1
公开(公告)日：2014-09-25
申请号：US14018287
申请日：2013-09-04
申请人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
发明人： Akira KATAYAMA , Masahiro TAKAHASHI , Tsuneo INABA , Hyuck Sang YIM , Dong Keun KIM , Byoung Chan OH , Ji Wang LEE
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
摘要翻译： 根据一个实施例，存储器包括存储单元阵列，其包括沿列方向布置的块，第一和第二主全局导线，每列从列方向上从存储单元阵列的第一端延伸到第二端，第一电阻 连接在存储单元阵列内部的第一和第二主要全局导电线之间的改变元件，从列方向上从存储单元阵列的第一端延伸到第二端的第一参考全局导电线，以及连接到存储单元阵列的第二电阻变化元件 到存储单元阵列外的参考全局导线。
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公开(公告)号：US20130020571A1
公开(公告)日：2013-01-24
申请号：US13549867
申请日：2012-07-16
IPC分类号： H01L29/12
CPC分类号： H01L29/7869 , H01L29/24 , H01L29/78618
摘要： Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
摘要翻译： 提供了能够实现所谓的常关断开关元件的晶体管的结构及其制造方法。 提供了通过提高晶体管的特性实现高速响应和高速操作的半导体器件的结构及其制造方法。 提供了一种高度可靠的半导体器件。 在其中半导体层，源极和漏极电极层，栅极绝缘层和栅极电极层以该顺序堆叠的晶体管中。 作为半导体层，含有铟，镓，锌和氧中的至少四种元素的氧化物半导体层，铟的组成比（原子百分比）为镓和a的组成比的2倍以上 使用锌的组成比。
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公开(公告)号：US20120305913A1
公开(公告)日：2012-12-06
申请号：US13584840
申请日：2012-08-14
IPC分类号： H01L29/24
CPC分类号： H01L29/66742 , H01L21/02422 , H01L21/02472 , H01L21/02483 , H01L21/02502 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02667 , H01L27/1225 , H01L29/66969 , H01L29/7869
摘要： A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
摘要翻译： 可以使用较大的衬底，并且可以通过形成具有高结晶度的氧化物半导体层来制造具有期望的高场敏性迁移率的晶体管，由此大尺寸显示装置，高性能半导体器件， 等可以投入实际使用。 在衬底上形成第一多组分氧化物半导体层，并在其上形成单组分氧化物半导体层; 然后通过在500℃至1000℃（包括端值）进行热处理从表面向内部进行晶体生长，优选550℃至750℃，从而使第一多组分氧化物半导体层 包括单晶区域和形成包括单晶区域的单组分氧化物半导体层; 并且包括单晶区域的第二多分量氧化物半导体层堆叠在包括单晶区域的单组分氧化物半导体层上。
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公开(公告)号：US20120063215A1
公开(公告)日：2012-03-15
申请号：US13191678
申请日：2011-07-27
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。
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公开(公告)号：US20120001179A1
公开(公告)日：2012-01-05
申请号：US13166073
申请日：2011-06-22
申请人： Shunpei YAMAZAKI , Masahiro TAKAHASHI , Takuya HIROHASHI , Katsuaki TOCHIBAYASHI , Yasutaka NAKAZAWA , Masatoshi YOKOYAMA
发明人： Shunpei YAMAZAKI , Masahiro TAKAHASHI , Takuya HIROHASHI , Katsuaki TOCHIBAYASHI , Yasutaka NAKAZAWA , Masatoshi YOKOYAMA
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/4908 , H01L29/78606 , H01L29/78693
摘要： It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. A semiconductor device having a stacked-layer structure of a gate insulating layer; a first gate electrode in contact with one surface of the gate insulating layer; an oxide semiconductor layer in contact with the other surface of the gate insulating layer and overlapping with the first gate electrode; and a source electrode, a drain electrode, and an oxide insulating layer which are in contact with the oxide semiconductor layer is provided, in which the nitrogen concentration of the oxide semiconductor layer is 2×1019 atoms/cm3 or lower and the source electrode and the drain electrode include one or more of tungsten, platinum, and molybdenum.
摘要翻译： 本发明的目的是提供一种具有稳定的电特性和高可靠性的氧化物半导体的半导体装置。 一种具有栅极绝缘层的叠层结构的半导体器件; 与所述栅极绝缘层的一个表面接触的第一栅电极; 与所述栅绝缘层的另一表面接触并与所述第一栅电极重叠的氧化物半导体层; 并且提供与氧化物半导体层接触的源电极，漏电极和氧化物绝缘层，其中氧化物半导体层的氮浓度为2×1019原子/ cm3以下，源电极和 漏极包括钨，铂和钼中的一种或多种。
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公开(公告)号：US20110156026A1
公开(公告)日：2011-06-30
申请号：US12976388
申请日：2010-12-22
CPC分类号： H01L29/66742 , H01L21/02422 , H01L21/02472 , H01L21/02483 , H01L21/02502 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02667 , H01L27/1225 , H01L29/66969 , H01L29/7869
摘要： A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
摘要翻译： 可以使用较大的衬底，并且可以通过形成具有高结晶度的氧化物半导体层来制造具有期望的高场敏性迁移率的晶体管，由此大尺寸显示装置，高性能半导体器件， 等可以投入实际使用。 在衬底上形成第一多组分氧化物半导体层，并在其上形成单组分氧化物半导体层; 然后通过在500℃至1000℃（包括端值）进行热处理从表面向内部进行晶体生长，优选550℃至750℃，从而使第一多组分氧化物半导体层 包括单晶区域和形成包括单晶区域的单组分氧化物半导体层; 并且包括单晶区域的第二多分量氧化物半导体层堆叠在包括单晶区域的单组分氧化物半导体层上。
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公开(公告)号：US20110101335A1
公开(公告)日：2011-05-05
申请号：US12912196
申请日：2010-10-26
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42364 , H01L29/42384 , H01L29/518 , H01L29/66969 , H01L29/78606 , H01L29/78696
摘要： An object is to provide a semiconductor device including an oxide semiconductor with stable electric characteristics can be provided. An insulating layer having many defects typified by dangling bonds is formed over an oxide semiconductor layer with an oxygen-excess mixed region or an oxygen-excess oxide insulating layer interposed therebetween, whereby impurities in the oxide semiconductor layer, such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O), are moved through the oxygen-excess mixed region or oxygen-excess oxide insulating layer and diffused into the insulating layer. Thus, the impurity concentration of the oxide semiconductor layer is reduced.
摘要翻译： 本发明的目的是提供一种包括具有稳定电特性的氧化物半导体的半导体器件。 在氧化物半导体层上形成具有以悬挂键为代表的许多缺陷的绝缘层，其间具有氧过剩混合区域或氧过剩氧化物绝缘层，由此氧化物半导体层中的诸如氢或水分的杂质（ 氢原子或包含氢原子如H 2 O的化合物）通过氧过剩混合区域或氧 - 过量氧化物绝缘层移动并扩散到绝缘层中。 因此，氧化物半导体层的杂质浓度降低。
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公开(公告)号：US20150340087A1
公开(公告)日：2015-11-26
申请号：US14811237
申请日：2015-07-28
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译： 根据一个实施例，电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。
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公开(公告)号：US20150269996A1
公开(公告)日：2015-09-24
申请号：US14722846
申请日：2015-05-27
申请人： Masahiro TAKAHASHI
发明人： Masahiro TAKAHASHI
IPC分类号： G11C13/00
CPC分类号： G11C13/0021 , G11C5/147 , G11C5/148 , G11C7/00 , G11C7/06 , G11C7/14 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C16/28 , G11C29/021 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes a first memory cell, a word line, a first bit line, first and second inverters, first to sixth MOS transistors, and a control circuit. The first transistor is connected to the first output terminal of the first inverter. The second transistor is connected to the second output terminal of the second inverter. The fifth transistor has a first current path whose one end is connected to the first voltage terminal of the first inverter. The sixth transistor has a second current path whose one end is connected to the third voltage terminal of the second inverter. The control circuit makes the first and second transistors a cutoff state by a first signal and makes the fifth and sixth transistors the cutoff state by a second signal in a standby state.
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公开(公告)号：US20140286082A1
公开(公告)日：2014-09-25
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译： 根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。 读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。 电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。
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