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公开(公告)号：US5712883A
公开(公告)日：1998-01-27
申请号：US581000
申请日：1996-01-03
IPC分类号： G01R31/319 , G06F1/10 , H03L7/07 , H03L7/081 , H04L7/00
CPC分类号： G01R31/31922 , G06F1/10 , H03L7/07 , H03L7/0812 , H04L7/0008
摘要： A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase lock loop controller. Matching pairs of transmission lines interconnect successive stages of the set. One transmission line of each pair connects the output of the first delay circuit of each stage to the input of the first delay circuit of a next stage of the set. The other transmission line of the pair connects the input of the second delay circuit of the stage to the input of the first delay circuit of the next stage. When the first delay circuit of the first stage of the set receives an input reference clock signal, that reference clock signal propagates through all the first delay circuits of each stage in succession. Whenever the input reference clock signal reaches a stage, it also travels back to the second delay circuit of the preceding stage. The phase lock loop controller in each stage adjusts the similar delay provided by its first and second delay circuits to phase lock the output second delay circuit to the input of the first delay circuit. Each stage also includes a frequency multiplier for doubling the frequency of its first input signal thereby to produce one of the spatially distributed local clock signals.
摘要翻译： 用于分配同步时钟信号的系统包括一组空间分布的去歪斜阶段。 每个级包括可调整的第一和第二延迟电路和一个锁相环控制器。 传输线的匹配对互连该组的连续阶段。 每对的一条传输线将每级的第一延迟电路的输出连接到该组的下一级的第一延迟电路的输入端。 该对的另一传输线将级的第二延迟电路的输入连接到下一级的第一延迟电路的输入。 当集合的第一级的第一延迟电路接收到输入参考时钟信号时，该参考时钟信号依次传播到每个级的所有第一延迟电路。 每当输入参考时钟信号达到一个阶段时，它也返回到前一级的第二延迟电路。 每个级中的锁相环控制器调节由其第一和第二延迟电路提供的类似延迟，以将输出第二延迟电路锁定到第一延迟电路的输入。 每个级还包括用于使其第一输入信号的频率加倍的倍频器，从而产生空间分布的本地时钟信号之一。
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22.发明授权Apparatus for performing logic and leakage current tests on a digital logic circuit 失效用于在数字逻辑电路上执行逻辑和漏电流测试的装置
公开(公告)号：US5696773A
公开(公告)日：1997-12-09
申请号：US639165
申请日：1996-04-25
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： G01R31/02 , G01R31/28 , G01R31/30 , G01R31/319
CPC分类号： G01R31/3004 , G01R31/31924
摘要： An apparatus for performing logic and leakage current tests on a logic circuit device under test (DUT) includes a local module for each terminal of the DUT. For performing logic test, each local module has a driver for supplying a logic signal input to the DUT terminal, a comparator for detecting the DUT output at the terminal, and a clamping circuit for limiting the voltage swing at the DUT terminal during the logic test. For performing a leakage current test, each local module includes a source for supplying a parametric signal to the DUT terminal. The voltage the parametric signal produces at the DUT terminal, as detected by the comparator, indicates the terminal's leakage current. The parametric signal source and the clamping circuit are connected to the DUT terminal through Schottky diodes. During a logic test the parametric signal source is isolated from the DUT terminal by reverse biasing the Schottky diodes linking the parametric signal source to the DUT terminal. Conversely, during a leakage current test, the clamping circuit is isolated from the DUT terminal by reverse biasing the Schottky diodes linking it to the DUT terminal. The Schottky diodes, when reverse biased, have very low capacitance and leakage current. Thus a DUT terminal leakage current measurement is not substantially influenced by leakage current through the clamping circuit and the edges of logic signal pulses are not substantially affected by capacitance added to the DUT terminal by the parametric signal source.
摘要翻译： 用于在待测逻辑电路器件（DUT）上执行逻辑和漏电流测试的装置包括用于DUT的每个端子的本地模块。 为了执行逻辑测试，每个本地模块具有用于提供输入到DUT端子的逻辑信号的驱动器，用于检测端子上的DUT输出的比较器和用于在逻辑测试期间限制DUT端子处的电压摆幅的钳位电路 。 为了进行漏电流测试，每个本地模块包括用于向DUT终端提供参数信号的源。 由比较器检测到的参数信号在DUT端产生的电压表示端子的漏电流。 参数信号源和钳位电路通过肖特基二极管连接到DUT端子。 在逻辑测试期间，通过将参考信号源链接到DUT端子的肖特基二极管反向偏置，参量信号源与DUT端子隔离。 相反，在泄漏电流测试期间，钳位电路通过将连接到DUT端子的肖特基二极管反向偏置而与DUT端子隔离。 当反向偏置时，肖特基二极管具有非常低的电容和漏电流。 因此，DUT端子泄漏电流测量基本上不受通过钳位电路的泄漏电流的影响，并且逻辑信号脉冲的边缘基本上不受由参数信号源添加到DUT端子的电容的影响。
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公开(公告)号：USD332915S
公开(公告)日：1993-02-02
申请号：US754690
申请日：1991-09-04
申请人： Norbert Hoell , Charles A. Miller
设计人： Norbert Hoell , Charles A. Miller
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公开(公告)号：US4919266A
公开(公告)日：1990-04-24
申请号：US362675
申请日：1989-06-09
CPC分类号： B65D71/14 , B65D2571/00141 , B65D2571/00444 , B65D2571/00543 , B65D2571/0066 , B65D2571/00753
摘要： An end wall display window particularly structured for use with a wraparound type carton in which a container matrix of, e.g., soft drink or beer cans, is sold. The display window structure preferably includes two wrap panels at each end of the carton, one on each wrap panel pair being connected to each of the carton's side walls. The two wrap panels of each pair are wrapped around portions of the outer surface of the end container in the matrix so that the wrap panels conform to the configuration of those container outer surface portions. The wrap panels are configured to define a window so that at least a portion of those end containers about which they are wrapped will be exposed to the sight of a casual viewer.
摘要翻译： 一种特别结构化的端壁展示窗，其特征在于与卷绕型纸箱一起使用，其中出售例如软饮料或啤酒罐的容器基质。 显示窗结构优选地在纸箱的每个端部包括两个包裹面板，每个包裹片对上的一个连接到每个纸箱的侧壁。 每对的两个包裹面板被卷绕在基质中端部容器的外表面的一部分，使得包裹面板符合那些容器外表面部分的构造。 包裹面板被配置成限定窗口，使得它们被包裹的那些端部容器的至少一部分将暴露于临时观察者的视线。
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公开(公告)号：US08646654B2
公开(公告)日：2014-02-11
申请号：US13399359
申请日：2012-02-17
申请人： Charles A. Miller
发明人： Charles A. Miller
CPC分类号： B65D71/36 , B65D5/5405 , B65D5/703 , B65D2571/00141 , B65D2571/0045 , B65D2571/00623 , B65D2571/0066 , B65D2571/00728
摘要： A package includes an article group formed of cylindrical articles disposed on their sides in a side-by-side parallel fashion, and a carton disposed around the group. The carton includes a top wall, opposed side walls, end walls and an article dispenser. The side walls are disposed alongside the ends of the articles while one end wall is disposed adjacent to the side wall of an endmost article. The dispenser is formed from the end and top walls and includes at least one retaining panel to hold all the articles in the carton until removed by the user.
摘要翻译： 一种包装物，其包括以并列方式设置在其侧面的圆柱形制品形成的物品组，以及围绕该组设置的纸箱。 纸箱包括顶壁，相对的侧壁，端壁和物品分配器。 侧壁沿着物品的端部设置，同时一个端壁邻近最后端物品的侧壁设置。 分配器由端壁和顶壁形成并且包括至少一个保持板，用于将所有的物品保持在纸箱中，直到使用者移除。
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公开(公告)号：US08614590B2
公开(公告)日：2013-12-24
申请号：US12844126
申请日：2010-07-27
申请人： Charles A. Miller
发明人： Charles A. Miller
CPC分类号： G01R31/2889 , G01R1/07314 , G01R1/07378 , G01R31/31905 , Y10T29/49117
摘要： A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads.
摘要翻译： 用于在集成电路（IC）测试器和要测试的IC的表面上的输入/输出，电源和接地焊盘之间提供信号路径的探针系统包括探针板组件，柔性电缆和一组探针， IC的I / O焊盘。 探针板组件包括一个或多个刚性衬底层，其具有形成在衬底层上或衬底层内的迹线和通孔，其提供将测试器连接到访问IC的一些衬垫的探针的相对低带宽的信号路径。 柔性电缆提供相对高带宽的信号路径，将测试仪连接到访问IC其他焊盘的探针。
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公开(公告)号：US08324725B2
公开(公告)日：2012-12-04
申请号：US11160477
申请日：2005-06-24
IPC分类号： H01L23/485 , H01L21/00 , H01L25/16 , H01L25/065
CPC分类号： H01L24/48 , H01L23/13 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48465 , H01L2224/4911 , H01L2224/73215 , H01L2224/73265 , H01L2224/85186 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01031 , H01L2924/01033 , H01L2924/01082 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2224/45099 , H01L2924/00012 , H01L2924/00
摘要： Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.
摘要翻译： 半导体管芯彼此堆叠地堆叠，使得沿着每个管芯的两个边缘定位的端子被暴露。 具有端子的模具的两个边缘可以沿相同的方向定向。 电连接可以将一个管芯上的端子连接到另一个管芯上的端子，并且堆叠可以设置在可以电连接管芯的端子的布线基板上。
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公开(公告)号：US08067951B2
公开(公告)日：2011-11-29
申请号：US12498862
申请日：2009-07-07
申请人： Charles A. Miller
发明人： Charles A. Miller
CPC分类号： G01R31/2889 , G01R1/07342
摘要： A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.
摘要翻译： 探针卡组件可以包括接口，其可以被配置为从测试仪接收测试用于测试电子设备的信号。 探针卡组件还可以包括用于接触电子设备的探针和用于将测试信号驱动到探针中的探针的电子驱动器电路。
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公开(公告)号：US07994803B2
公开(公告)日：2011-08-09
申请号：US12569584
申请日：2009-09-29
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： G01R31/00
CPC分类号： G01R35/005 , G01R31/3016 , G01R31/31723 , G01R31/318511 , G01R31/3191 , G01R31/31937
摘要： A calibration substrate includes a plurality of input terminals, a detector coupled to the input terminals, and an output terminal. The calibration substrate can be used for calibrating and/or deskewing communications channels.
摘要翻译： 校准基板包括多个输入端子，耦合到输入端子的检测器和输出端子。 校准基板可以用于校准和/或去歪斜通信通道。
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公开(公告)号：US20110115512A1
公开(公告)日：2011-05-19
申请号：US11180247
申请日：2005-07-12
申请人： Charles A. Miller
发明人： Charles A. Miller
CPC分类号： G01R1/073 , G01R1/06766 , G01R1/06772
摘要： Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
摘要翻译： 这里描述的是提供用于在集成电路（IC）和IC测试器的接合焊盘之间传送高频信号的信号路径的探针卡组件。 通过沿着信号路径适当地分布，调整和阻抗匹配电阻，电容和电感阻抗值来优化探针卡组件的频率响应，使得互连系统作为适当调节的巴特沃斯或切比雪夫滤波器。
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