公开(公告)号：US10727249B2

公开(公告)日：2020-07-28

申请号：US16410992

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US10446681B2

公开(公告)日：2019-10-15

申请号：US15645202

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L27/11524 ,  H01L29/792 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/10 ,  H01L21/321

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190051661A1

公开(公告)日：2019-02-14

申请号：US15675223

申请日：2017-08-11

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20180204849A1

公开(公告)日：2018-07-19

申请号：US15409412

申请日：2017-01-18

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518 ,  H01L29/7926

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US11678483B2

公开(公告)日：2023-06-13

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  H10B41/27 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  G06F3/0688 ,  G11C8/14 ,  G11C16/0466 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20220278126A1

公开(公告)日：2022-09-01

申请号：US17748641

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210408039A1

公开(公告)日：2021-12-30

申请号：US17468170

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US20210343736A1

公开(公告)日：2021-11-04

申请号：US16862150

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Chris M. Carlson ,  Richard J. Hill ,  Davide Resnati

IPC: H01L27/11556 ,  H01L27/06 ,  H01L27/11582 ,  G11C5/02

Abstract: An electronic structure comprising stacks comprising alternating dielectric materials and conductive materials in a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks and in a pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material in the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials in the cell region of the electronic structure. The cell high-k dielectric material adjoins a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, as are related electronic devices, systems, and methods of forming an electronic device.

公开(公告)号：US11037951B2

公开(公告)日：2021-06-15

申请号：US16580751

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Ugo Russo

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210175247A1

公开(公告)日：2021-06-10

申请号：US16705388

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/3115 ,  H01L21/3215

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.