公开(公告)号：US09711457B2

公开(公告)日：2017-07-18

申请号：US14733330

申请日：2015-06-08

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

公开(公告)号：US20160013134A1

公开(公告)日：2016-01-14

申请号：US14733330

申请日：2015-06-08

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

公开(公告)号：US09209166B2

公开(公告)日：2015-12-08

申请号：US14665718

申请日：2015-03-23

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/304 ,  H01L21/78 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/05552

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releasably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Abstract translation: 堆叠的半导体器件，半导体组件，堆叠半导体器件的制造方法以及制造半导体组件的方法。 半导体组件的一个实施例包括具有可释放地附接到临时载体，背面和主动侧的多个第一裸片的有源侧的薄化半导体晶片。 单独的第一裸片具有集成电路，首先通过芯片互连电连接到集成电路，以及暴露在晶片背面的互连触点。 组件还包括多个分开的第二模具，其附接到正面上的对应的第一模具，其中各个第二模具具有集成电路，通过电连接到集成电路的模具互连和后侧的接触点，并且其中所述个体 第二模具具有大约小于100微米的厚度。

公开(公告)号：US08766458B2

公开(公告)日：2014-07-01

申请号：US13682019

申请日：2012-11-20

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L29/40 ,  H01L21/4763 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/7684 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/525 ,  H01L23/544 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/81 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die.

Abstract translation: 本文公开了采用管芯到管芯互连的堆叠的微电子管芯以及相关的系统和方法。 在一个实施例中，微电子管芯的堆叠系统包括第一微电子管芯，附接到第一管芯的第二微电子管芯和将第一管芯与第二管芯电耦合的管芯到管芯互连。 第一模具包括背面表面，背面表面中的表面凹陷和位于表面凹陷内的第一金属触点。 第二模具包括前侧表面和位于前侧表面处并与第一模具的第一金属触点对准的第二金属触点。 模 - 芯互连将第一管芯的第一金属接触与第二管芯的第二金属接触电耦合，并且包括至少部分地填充第一管芯的表面凹陷的可流动的金属层。