公开(公告)号：US10153008B2

公开(公告)日：2018-12-11

申请号：US15133986

申请日：2016-04-20

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G11C8/16 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

公开(公告)号：US10026459B2

公开(公告)日：2018-07-17

申请号：US15692783

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

公开(公告)号：US09892767B2

公开(公告)日：2018-02-13

申请号：US15043236

申请日：2016-02-12

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

公开(公告)号：US20170236564A1

公开(公告)日：2017-08-17

申请号：US15043236

申请日：2016-02-12

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

公开(公告)号：US09659605B1

公开(公告)日：2017-05-23

申请号：US15133861

申请日：2016-04-20

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/14 ,  G11C7/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C7/1012 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F13/1663 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/005 ,  G11C2211/5641

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

公开(公告)号：US20230333744A1

公开(公告)日：2023-10-19

申请号：US18211356

申请日：2023-06-19

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G11C8/12 ,  G11C7/10 ,  G06F15/78 ,  G06F3/06 ,  G11C29/28

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：US20230043636A1

公开(公告)日：2023-02-09

申请号：US17971300

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20190355406A1

公开(公告)日：2019-11-21

申请号：US16526198

申请日：2019-07-30

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny

IPC: G11C11/402 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/10 ,  G11C5/02

Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

公开(公告)号：US10453502B2

公开(公告)日：2019-10-22

申请号：US15090301

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C11/4074 ,  G11C8/12 ,  G06F12/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a power budget operation associated with the memory operation to be performed, based at least in part on information stored in a budget area, such as a register. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation, or incremented upon completion of an operation, associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory (PIM) operation.

公开(公告)号：US10418092B2

公开(公告)日：2019-09-17

申请号：US15961374

申请日：2018-04-24

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush

IPC: G11C7/10 ,  G11C11/4091 ,  G11C16/28 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4096

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.