公开(公告)号：US11907547B2

公开(公告)日：2024-02-20

申请号：US17729207

申请日：2022-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Xiaojiang Guo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/32 ,  G06F1/3206 ,  G11C7/22 ,  G11C7/10 ,  G06F1/3215 ,  G11C16/30 ,  G11C5/14 ,  G11C16/04 ,  H01L25/065 ,  G06F119/06

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3215 ,  G06F3/0631 ,  G06F3/0683 ,  G11C5/14 ,  G11C7/1045 ,  G11C7/22 ,  G11C16/30 ,  G11C16/32 ,  G06F2119/06 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06562

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

公开(公告)号：US20240055058A1

公开(公告)日：2024-02-15

申请号：US18229249

申请日：2023-08-02

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry

IPC: G11C16/30 ,  G11C5/06

CPC classification number: G11C16/30 ,  G11C5/06

Abstract: A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

公开(公告)号：US20230350587A1

公开(公告)日：2023-11-02

申请号：US18137002

申请日：2023-04-20

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Daniel J. Hubbard ,  Suresh Rajgopal

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

公开(公告)号：US11681474B2

公开(公告)日：2023-06-20

申请号：US17562590

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F1/14

CPC classification number: G06F3/0659 ,  G06F1/14 ,  G06F3/0604 ,  G06F3/0673 ,  G11C7/1009

Abstract: A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

公开(公告)号：US20230060310A1

公开(公告)日：2023-03-02

申请号：US17464868

申请日：2021-09-02

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Luigi Pilolli ,  Biagio Iorio

IPC: G06F3/06 ,  G06F1/04

Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

公开(公告)号：US11520497B2

公开(公告)日：2022-12-06

申请号：US17110103

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F12/0802

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

公开(公告)号：US20220121399A1

公开(公告)日：2022-04-21

申请号：US17562590

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/06 ,  G06F1/14 ,  G11C7/10

Abstract: A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

公开(公告)号：US11200001B2

公开(公告)日：2021-12-14

申请号：US16875464

申请日：2020-05-15

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Parry

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.

公开(公告)号：US20210334020A1

公开(公告)日：2021-10-28

申请号：US16855655

申请日：2020-04-22

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  William C. Filipiak

IPC: G06F3/06 ,  G06K9/62

Abstract: A set of memory management operations is executed on multiple memory dies of a memory sub-system. Voltage parameter levels corresponding to the set of memory management operations are determined. Information representing a voltage parameter level and a corresponding portion of the set of memory management operations is determined based on the set of voltage parameter levels. A request is received from a host system to execute a target portion of a memory management operation. First information corresponding to the target portion of the memory management operation is identified. Based on the first voltage parameter level, power management action is performed.

公开(公告)号：US20240233836A1

公开(公告)日：2024-07-11

申请号：US18583066

申请日：2024-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jeremy Binfet

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/48011 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2224/4903 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1438

Abstract: A memory device might include registers configured to store expected peak current magnitudes corresponding to a plurality of memory devices containing the memory device, and a controller configured to cause the memory device to determine whether to initiate a next phase of an access operation in response to at least a first sum of an expected peak current magnitude for the next phase of the access operation in a selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a first current demand budget, and a second sum of the expected peak current magnitude for the next phase of the access operation in the selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a second, lower, current demand budget.